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for n t686 6 7 fg / n t686 6 7 hfg/ n t686 6 7 ufg scaler flat panel monitor controller v 1.5 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 2 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. table of contents 1. revision history ................................ ................................ ................................ ............... 4 2. features ................................ ................................ ................................ .............................. 5 3. general des cription ................................ ................................ ................................ ...... 7 4. block diagram ................................ ................................ ................................ .................. 8 5. pinout information ................................ ................................ ................................ .......... 9 5.1. p in d iagram ................................ ................................ ................................ ..................... 9 5.2. p in a ssignment ................................ ................................ ................................ .............. 10 5.3. p in d escription ................................ ................................ ................................ ............. 15 6. funct ional description ................................ ................................ ............................... 17 6.1. p ower c ontrol ................................ ................................ ................................ ............ 17 6.2. a nalog to d igital c onverter (adc) ................................ ................................ ............ 17 6.3. dvi r eceiver ................................ ................................ ................................ ................. 18 6.4. g raphic p ort c apture i nterface ................................ ................................ ................ 18 6.5. v ideo p ort c apture i nterface ................................ ................................ .................... 19 6.6. a uto t une ................................ ................................ ................................ ...................... 19 6.7. v ideo p rocessor ................................ ................................ ................................ .......... 19 6.8. s ync p rocessor ................................ ................................ ................................ ........... 21 6.9. osd f unction ................................ ................................ ................................ ............... 24 6.10. dpll c lock c ontrol ................................ ................................ ................................ .... 32 6.11. display interface ................................ ................................ ................................ .... 33 6.11.1. scaler display data ................................ ................................ ................................ .... 33 6.11.2. single/dual pixel lvds transmitter ................................ ................................ ............. 34 6.12. m iscellaneous ................................ ................................ ................................ .............. 36 6.12.1. pwm output ................................ ................................ ................................ ............... 36 6.13. mcu i nterface ................................ ................................ ................................ .............. 37 6.13.1. irqn interrupt sources ................................ ................................ ............................... 37 6.14. 8031 o n - c hip m icrocontroller ................................ ................................ ................... 38 7. electrical specifica tions ................................ ................................ .......................... 39 7.1. dc e lectrical c haracteristics ................................ ................................ ................... 39 7.2. ac e lectrical c haracteristics ................................ ................................ ................... 44 8. registers mapping ................................ ................................ ................................ ......... 47 8.1. adc i nterface ................................ ................................ ................................ ............... 48 8.2. dvi i nput c ontrol 1 ................................ ................................ ................................ ...... 51 8.3. p re - p attern c ontrol ................................ ................................ ................................ ... 53 8.4. g raphic p ort c ontrol ................................ ................................ ................................ . 53 8.5. v ideo p ort c ontrol ................................ ................................ ................................ ..... 61 8.6. c olor space conversio n c ontrol ................................ ................................ .............. 63 8.7. v ideo p ort c apture c ontrol ................................ ................................ ...................... 64 8.8. b ack e nd i m age p rocessing ................................ ................................ ......................... 65 8.9. n oise r eduction f ilter c ontrol ................................ ................................ ................. 67 8.10. g eneral p urpose i nput o utput (gpio) ................................ ................................ ....... 6 8 8.11. pwm o utput ................................ ................................ ................................ ................. 69 8.12. o n s creen d isplay r egisters ................................ ................................ ...................... 71 8.13. s ource h sync d igital pll c o ntrol ................................ ................................ ............. 87 8.14. i ndex p ort a ccess c ontrol ................................ ................................ ......................... 90 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 3 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8.15. a uto g ain /g auge a ccess w indow c ontrol ................................ ................................ 91 8.16. d isplay d igital pll c ontrol ................................ ................................ ........................ 93 8.17. g raphic i nput g auge ................................ ................................ ................................ .... 95 8.18. p roduct id ................................ ................................ ................................ .................... 95 8.19. p ower c ontrol ................................ ................................ ................................ ............ 96 8.20. a uto t une ................................ ................................ ................................ ...................... 96 8.21. b right f rame d isplay r egisters ................................ ................................ ............... 102 8.22. dvi i nput c ontrol 2 ................................ ................................ ................................ .... 104 8.23. d isplay p ort c ontrol ................................ ................................ ................................ 105 8.24. s ync p rocessor ................................ ................................ ................................ .......... 115 8.25. lvds o utput c ontrol ................................ ................................ ................................ 123 8.26. s rgb c ontrol ................................ ................................ ................................ ............ 126 8.27. h igh - bandwidth d igital c ontent p rotection s ystem ................................ .............. 131 8.28. d ithering f unction 2 ................................ ................................ ................................ .. 137 8.29. h orizontal n on - l i near s caling f unction ................................ ................................ . 140 8.30. b right f rame b order f unction ................................ ................................ ................. 141 8.31. y/c p eaking c ontrol ................................ ................................ ................................ .. 144 8.32. ace c ontrol ................................ ................................ ................................ ............... 145 8.33. c olor m anagement ................................ ................................ ................................ .... 147 8.34. dbc ................................ ................................ ................................ .............................. 150 9. ordering information ................................ ................................ ................................ 153 package information ................................ ................................ ................................ ............. 154 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 4 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 1. revision history nt 686 6 7 specification revision history version content da ta 0. 1 first version released oct . 200 7 0.2 d elete tcon feature dec . 2007 1.0 release feb. 2008 1.1 register , ac/dc spec. update mar. 2008 1.2 a dd chip surface temperature mar. 2008 1.3 0x150~0x153 reg. update 0x13a, 0x13b remove mar. 2008 1.4 bloc k diagram update non - linear ace reg. update nr reg. 0x068 , 0x06a update apr. 2008 1.5 0x338 update add u type spec. may. 2008 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 5 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 2. features analog graphic input ? support rgb inputs 1440x900 @ 75 hz for NT68667FG , 1680x1050 @ 75 hz for nt68667hfg , 1920x1080 @ 75 hz for nt68667ufg or ypbpr ( 1080p ) inputs ? triple 8bit adcs (0.5 5 ~ 0.9 v) with 500mhz bandwidth ? 1 66 mhz (nt68667 fg)/188 mhz(nt68667 h fg) /190 mhz(nt68667 u fg) hpll with 64 steps phase adjust for each rgb channel ? auto offset for component video ? support s both non - in terlaced and interlaced input signals ? adc bandwidth adjust : 500m,450m,400m,350m,300m,250m,150m,75m digital graphic and video inputs ? dvi receiver up to 165mhz with hdcp with hdcp 280 bytes sram ? supports itu - r bt.656 8 - bit input format video processing ? zoom and shrink engineer with non - linear scaling in horizontal direction for wide screen panels ? the 3 rd generation bright frame with adaptive contrast control, 24 color tones adjustment , srgb real color engine and edge enhancement functions ? adjustable sharpne ss setting ? support dbc to save system operation power ? fix ed 10 bit dither lsb & 10 - 8 dither enable ? text enahncem ent ? enhance ghost cancellation sync processor ? support ttl sync - on - green (sog) (including sync slicer) ? polarity detection ? frequency measurement ? fast mode change detection ? interlace or non - interlace input detection ? separate or composite sync auto switching (including sync separator) internal osd ? programmable multi - color ram font as well as a bitmapped graphical osd are supported ? provide 1 ,2, 3 /4 bits/pixel ram fonts ? optional 10x18, 12x18, 10x16, 12x16 dot matrix ? internal sram allows up to 2048 characters, with programmable osd frame size. width is 64 column, and height is 32 row ? programmable shadow or border control for each character by each row ? programmable blinking effects for each character ? spacing control to avoid expansion distortion ? supports simultaneous display of up to 4 osd windows ? maximum 4 times of global zoom for horizontal and vertical axis ? separate row zoom control ? support flexible fg or bg optional transparent, translucent, and opaque effects ? 256 palette with 64k color selectable ? top - bottom flip, left - right mirror and 90 degree / 270 degree rotated ? flexible fade - in, fade - out effect free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 6 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. i splitting osd frame supported i gradient fade - in/fade ? out i i nser t variable space by row i total pr ovide 15k byt e ra m size display output i support 8/6bit single/dual port lvds panel up to 1440x900@75 for n t68667fg , 1680x1050@75 for n t68667 h fg and 1920x1080@75 for n t68667 u fg i lvds su pport up to 190mhz i all of ou tput keep ? low ? after power up built - in dual pixel lvds transmitter i integrate the dual port, 4 data channel and clock - out low - voltage differential lvds transmitter to supports single or dual pixel 6/8 - bit display data transmission i suited for vga, svga, xga and dual pixel sx ga, ws xga display transmission from controller to display with very low emi embedded microcontroller i external spi program memory supported i 1 uart, 2 timers, 2 external interrupts i 2 x i2c master/slavers for ddc2bi/2b+/ci and edid functions i i/os: 4 x 7bits adc, 10 x pwm, totally 3 5 adjustable i/os i support ddc 5v/3.3v compatible power i 3.3v/1.8v power supply i normal operate less than 1 w i embedded 3.3 to 1.8 ldo package i qfp 128 pin free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 7 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 3. general description the nt 686 6 7 is a highly integrated flat pan el display controller that interfaces analog, digital, and video inputs. it combines a triple adc, a dvi compliant tmds receiver, a digital yuv receiver, a high quality zoom and shrink engine , a multi - color on screen display (osd) controller , an advanced color engine , and many other functions in a single chip. it provides the user with a simple, flexible and cost - effective solution for various flat panel display products. the nt 686 6 7 o perates at frequencies up to 166mhz/ 188 mhz /190mhz suitable for lcd mo nitor up to 1440x900/1680x1050/1920x1080 re solution. the nt 686 6 7 also h as a built - in noise reduction function to provide more stable video quality, spread spectrum to provide low emi solution, srgb for video color space convert and post pattern for manufac ture test. the display provided single/double pixel clock lvds interface. in addition, nt 686 6 7 includes an integrated 8 - bit microcontroller (mcu). it contains an 8 - bit 8031 micro - controller, 3,840 ? bytes internal data memory, four 7 - bit resolution a/d conv erter, 10 - channel 8 - bit resolution pwm dac, two16 - bit timer/counters, and a uart. except those, it has two - channel hardware ddc solution, and vesa 2bi/2b+ master/slave i 2 c bus interface. figure 1 nt 686 6 7 system design example scaler vga in dvi in tv decoder s - video in cvbs in yuv ( itu 656 ) serial flash memory nt 686 67 lvds free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 8 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 4. block diagram graphic capture / measurement triple adc tmds rx yuv to rgb mcu digital tmds sync processor sog slicer sogi hs / vs lvds transmitter pre - pattern generator ssc clock generation reference crystal scaling osd controller osd rams bf srgb gamma / 10 - 8 dithering display control post pattern generator hpll adc _ hs over - sampling clock data over sampling external flash memory video capture measurement yuv digital video in _ yuv _ hs / in _ yuv _ vs / in _ field ddc 2 bi * 2 analog rgb 8 - 6 dithering figure 4 - 1 functional block diagram free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 9 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 5. pinout information 5.1. pin diagram 75 74 73 72 71 70 69 80 79 78 77 76 82 81 84 83 87 86 85 88 89 90 68 67 66 65 95 94 93 92 91 100 99 98 97 96 102 101 11 10 9 8 7 6 5 16 15 14 13 12 18 17 20 19 23 22 21 24 25 26 4 3 2 1 31 30 29 28 27 36 35 34 33 32 38 37 rstb dvdd dgnd rx 2 + rx 2 - avcc rx 1 + rx 1 - agnd rx 0 + rx 0 - agnd rxc + rxc - avcc rext pvcc pgnd bin 1 + bin 1 - sog 1 i gin 1 + gin 1 - rin 1 + rin 1 - adc _ vaa adc _ gnda pc 2 pd 6 pb 3 / adc 3 / inte 1 p 31 / txd p 30 / rxd pb 2 / adc 2 / inte 0 pb 7 */ addc _ sda * pb 6 */ addc _ scl * pa 3 / pwm 5 pa 4 */ pwm 6 * pa 5 */ pwm 7 * pc 6 dgnd / cgnd dgnd / cgnd dgnd / cgnd dgnd / cgnd dgnd / cgnd dgnd / cgnd dgnd / cgnd dgnd / cgnd dgnd / cgnd dgnd / cgnd dgnd / cgnd dvdd nc t 0 m t 0 p t 1 m t 1 p t 2 m t 2 p tclk 1 m tclk 1 p t 3 m t 3 p dgnd / cgnd t 4 m t 4 p t 5 m t 5 p t 6 m t 6 p tclk 2 m tclk 2 p t 7 m t 7 p pa 1 / pwm 3 pa 2 / pwm 4 pa 0 / pwm 2 nt 68667 fg figure 5.1 - 1 nt68667 pin diagram free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 10 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 5.2. pi n assignment no. pin type operate voltage definition 1 rstb i 0 ~ 3. 47 v active - low reset input; with schmitt trigger input 2 dvdd power 3.15v ~ 3.47v micro - controller +3.3v power supply input 3 d gnd power 0v micro - controller power ground 4 rx2+ i 0.15 ~ 1.2v tmds input channel 2+ 5 rx2 - i 0.15 ~ 1.2v tmds input channel 2 - 6 avcc power 3.15v ~ 3.47v tmds analog vcc must be set to 3.3v. 7 rx1+ i 0.15 ~ 1.2v tmds input channel 1+ 8 rx1 - i 0.15 ~ 1.2v tmds input channel 1 - 9 agnd power 0v tmds analo g gnd. 10 rx0+ i 0.15 ~ 1.2v tmds input channel 0+ 11 rx0 - i 0.15 ~ 1.2v tmds input channel 0 - 12 agnd power 0v tmds analog gnd. 13 rxc+ i 0.15 ~ 1.2v tmds input clock pair 14 rxc - i 0.15 ~ 1.2v tmds input clock pair 15 avcc power 3.15v ~ 3.47v t mds analog vcc must be set to 3.3v. 16 rext i external termination resistor. a 1% 470 resistor must be connected from this pin to avcc. notes: if this resistor not 1% , the compatibility is worse than 1% resistor . 17 pvcc power 3.15v ~ 3.47v tmds pl l analog vcc must be set to 3.3v. 18 pgnd power 0v tmds pll analog gnd. 19 bin1+ i b channel positive analog video input 20 bin1 - i b channel negative analog video input 21 sogi1 i vga port sync on green input with schmitt trigger 22 gin1+ i g ch annel positive analog video input 23 gin1 - i g channel negative analog video input 24 rin1+ i r channel positive analog video input 25 rin1 - i r channel negative analog video input 26 adc_vaa power 3.15v ~ 3.47v adc analog power supply 27 adc_gnda power 0v adc analog ground 28 pc2 i/o 0 ~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input 29 pd6 i/o 0 ~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input pb3 i/o 0 ~ 3. 47 v i/o pin; push - pull structure with schmitt trigger i nput adc3 i 0 ~ 3. 47 v a/d converter input - 3; hi - z input 30 inte1 i 0 ~ 3. 47 v external interrupt input 1; schmitt trigger input 31 p31 i/o 0 ~ 3. 47 v gpio port - 31 of micro - processor f8031 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 11 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. txd o 0 ~ 3. 47 v uart tx data output of micro - processor f8031 p 30 i/o 0 ~ 3. 47 v gpio port - 30 of micro - processor f8031 32 rxd i 0 ~ 3. 47 v uart rx data input of micro - processor f8031 pb2 i/o 0 ~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input adc2 i 0 ~ 3. 47 v a/d converter input - 2; hi - z input 33 inte0 i 0 ~ 3. 47 v external interrupt input 0, schmitt trigger input pb7* i/o 0 ~ 5 .25 v i/o pin; open - drain with schmitt trigger input 34 a ddc_sda * i/o 0 ~ 5 .25 v 5v open - drain serial data i/o pin for the vga ddc port and the slave/master i 2 c - bus port pb6* i/o 0 ~ 5 .25 v 5v i/o pin; open - drain with schmitt trigger input 35 a ddc_scl * i/o 0 ~ 5 .25 v 5v open - drain serial clock i/o pin for the vga ddc port and the slave/master i 2 c - bus port pa3 i/o 0 ~ 3. 47 v i/o pin; schmitt trigger input 36 pwm5 o 0 ~ 3. 47 v pwm - type d/a converter; 3.3v push - pull structure pa4* i/o 0 ~ 5 .25 v i/o pin; open - drain structure with schmitt trigger input 37 pwm6* o 0 ~ 5 .25 v pwm - type d/a converter; 5v open - drain structure pa5* i/o 0 ~ 5 .25 v i/o pin; open - drain structure with schm itt trigger input 38 pwm7* o 0 ~ 5 .25 v pwm - type d/a converter; 5v open - drain structure pa6* i/o 0 ~ 5 .25 v i/o pin; open - drain structure with schmitt trigger input 39 pwm8* o 0 ~ 5 .25 v pwm - type d/a converter; 5v open - drain structure pa7* i/o 0 ~ 5 .25 v i/o pin; open - drain structure with schmitt trigger input 40 pwm9* o 0 ~ 5 .25 v pwm - type d/a converter; 5v open - drain structure 41 hsynci i 0 ~ 5 .25 v vga port channel horizontal sync input with schmitt trigger 42 vsynci o 0 ~ 5 .25 v vga port channel vertica l sync input with schmitt trigger 43 pll_ gnd power 0v core logic ground pin for pll. 44 dgnd/cgnd power 0v digital ground/ core logic ground 45 pll_ vdd power 1.6v ~ 2.0v internal hpll power supply (1.8v) output . external capacitor (0.1uf and 100 uf) connected is recommended. pb5* i/o 0 ~ 5 .25 v 5v i/o pin; open - drain with schmitt trigger input 46 d ddc_sda*/ i/o 0 ~ 5 .25 v 5v open - drain serial data i/o pin for the dvi ddc port and the slave/master i 2 c - bus port pb4* i/o 0 ~ 5 .25 v 5v i/o pin; open - d rain with schmitt trigger input 47 d ddc_scl*/ i/o 0 ~ 5 .25 v 5v open - drain serial clock i/o pin for the dvi ddc port and the slave/master i 2 c - bus port 48 pd5 i/o 0 ~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input p35 i/o 0 ~ 3. 47 v gpio po rt - 35 of micro - processor f8031 49 t1 i 0 ~ 3. 47 v counter/timer t1 input of micro - processor f8031 p34 i/o 0 ~ 3. 47 v gpio port - 34 of micro - processor f8031 50 t0 i 0 ~ 3. 47 v counter/timer t0 input of micro - processor f8031 51 dvdd power 3.15v ~ 3.47v displa y digital power supply 52 cvdd power 1.6v ~ 2.0v core logic power supply (1.8v) pin. external capacitor (0.1uf) connected is recommended. 53 dvdd power 3.15v ~ 3.47v display digital power supply free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 12 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 54 v0 i 0 ~ 3. 47 v video data input 55 v1 i 0 ~ 3. 47 v vide o data input 56 v2 i 0 ~ 3. 47 v video data input 57 v 3 i 0 ~ 3. 47 v video data input 58 v4 i 0 ~ 3. 47 v video data input 59 v5 i 0 ~ 3. 47 v video data input 60 v6 i 0 ~ 3. 47 v video data input 61 v7 i 0 ~ 3. 47 v /video data input 62 yuv_clk i 0 ~ 3. 47 v vi deo port clock 63 nc 64 dgnd/cgnd power 0v digital ground/ core logic ground pa0 i/o 0 ~ 3. 47 v i/o pin; schmitt trigger input 65 pwm2 o 0 ~ 3. 47 v pwm - type d/a converter; 3.3v push - pull structure pa2 i/o 0 ~ 3. 47 v i/o pin; schmitt trigger input 66 pwm4 o 0 ~ 3. 47 v pwm - type d/a converter; 3.3v push - pull structure pa1 i/o 0 ~ 3. 47 v i/o pin; schmitt trigger input 67 pwm3 o 0 ~ 3. 47 v pwm - type d/a converter; 3.3v push - pull structure 68 t7p lvdso 1.2 0.10 v ~ 1.2 0.22 v positive lvds differentia l data output of channel 7 69 t7m lvdso 1.2 0.10 v ~ 1.2 0.22 v negative lvds differential data output of channel 7 70 tclk2p lvdso 1.2 0.10 v ~ 1.2 0.22 v positive lvds differential clock 2 output 71 tclk2m lvdso 1.2 0.10 v ~ 1.2 0.22 v negat ive lvds differential clock 2 output 72 t6p lvdso 1.2 0.10 v ~ 1.2 0.22 v positive lvds differential data output of channel 6 73 t6m lvdso 1.2 0.10 v ~ 1.2 0.22 v negative lvds differential data output of channel 6 74 t5p lvdso 1.2 0.10 v ~ 1.2 0.22 v positive lvds differential data output of channel 5 75 t5m lvdso 1.2 0.10 v ~ 1.2 0.22 v negative lvds differential data output of channel 5 76 t4p lvdso 1.2 0.10 v ~ 1.2 0.22 v positive lvds differential data output of channel 4 77 t4m lvdso 1.2 0.10 v ~ 1.2 0.22 v negative lvds differential data output of channel 4 78 dgnd/cgnd power 0v digital ground/ core logic ground free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 13 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 79 t3p lvdso 1.2 0.10 v ~ 1.2 0.22 v positive lvds differential data output of channel 3 80 t3m lvdso 1.2 0.10 v ~ 1.2 0.22 v negative lvds differential data output of channel 3 81 tclk1p lvdso 1.2 0.10 v ~ 1.2 0.22 v positive lvds differential clock 1 output 82 clk1m lvdso 1.2 0.10 v ~ 1.2 0.22 v negative lvds differential clock 1 output 83 t2p lvd so 1.2 0.10 v ~ 1.2 0.22 v positive lvds differential data output of channel 2 84 t2m lvdso 1.2 0.10 v ~ 1.2 0.22 v negative lvds differential data output of channel 2 85 t1p lvdso 1.2 0.10 v ~ 1.2 0.22 v positive lvds differential data output of channel 1 86 t1m lvdso 1.2 0.10 v ~ 1.2 0.22 v negative lvds differential data output of channel 1 87 t0p lvdso 1.2 0.10 v ~ 1.2 0.22 v positive lvds differential data output of channel 0 88 t0m lvdso 1.2 0.10 v ~ 1.2 0.22 v negative lvds di fferential data output of channel 0 89 nc 90 dvdd power 3.15v ~ 3.47v display digital power supply 91 dgnd/cgnd power 0v digital ground/ core logic ground 92 dgnd/cgnd power 0v digital ground/ core logic ground 93 dgnd/cgnd power 0v digital ground/ core logic ground 94 dgnd/cgnd power 0v digital ground/ core logic ground 95 dgnd/cgnd power 0v digital ground/ core logic ground 96 dgnd/cgnd power 0v digital ground/ core logic ground 97 dgnd/cgnd power 0v digital ground/ core logic ground 98 dgnd/ cgnd power 0v digital ground/ core logic ground 99 dgnd/cgnd power 0v digital ground/ core logic ground 100 dgnd/cgnd power 0v digital ground/ core logic ground 101 dgnd/cgnd power 0v digital ground/ core logic ground 102 pc6 i/o 0~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input 103 pc7 i/o 0~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input 104 spi_c e o 0~ 3. 47 v external flash spi chip enable 105 spi_so i 0~ 3. 47 v external flash spi chip serial data output 106 spi_si o 0 ~ 3. 47 v external flash spi data serial data input free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 14 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 107 spi_clk o 0~ 3. 47 v external flash spi clock 108 pd4 i/o 0~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input 109 dgnd power 0v digital ground 110 nc 111 ad0 i/ o 0~ 3. 47 v slave addres s d0 112 ad1 i/ o 0~ 3. 47 v slave address d1 113 int_vso o 0~ 3. 47 v internal vertical sync output, this signal is by - pass the sync - processor 114 int_hso o 0~ 3. 47 v internal horizontal sync output, this signal is by - pass the sync - processor 115 cvdd power 1.6v ~ 2.0v core logic power supply (1.8v) pin. external capacitor (0.1uf) connected is recommended. 116 nc 117 pwm a* o 0~ 3. 47 v pwm type output open - drain structure 118 pwm b* o 0~ 5 .25 v pwm type output open - drain structure 119 cvdd power 1.6v ~ 2.0 v core logic power supply (1.8v) pin. external capacitor (0.1uf) connected is recommended. 120 pc0* i/o 0~ 5 .25 v i/o pin; 5v open - drain structure with schmitt trigger input 121 pc1* i/o 0~ 5 .25 v i/o pin; 5v open - drain structure with schmitt trigger input pc3 i/o 0~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input 122 pwm0 o 0~ 3. 47 v pwm - type d/a converter; push - pull structure pc4 i/o 0~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input 123 pwm1 o 0~ 3. 47 v pwm - type d/a conver ter; push - pull structure 124 pc5 i/o 0~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input 125 pb1/adc1 i/o 0~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input a/d converter input - 1; hi - z input 126 pb0/adc0 i/o 0~ 3. 47 v i/o pin; push - pull structure with schmitt trigger input a/d converter input - 0; hi - z input 127 osc i i 12 ~15 mhz external crystal osc output 128 osc o o 12 ~15 mhz external crystal osc input table 5.2 - 1 pin list free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 15 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 5.3. pin description system interface pin type definition rst b i system reset graphic analog interface pin type definition adc_gnda power adc analog ground adc_vaa power adc analog power supply bin1+ i b channel positive analog video input bin1 - i b channel negative analog video input sogi1 i vga port 1 sync on green input with schmitt trigger gin1+ i g channel positive analog video input gin1 - i g channel negative analog video input rin1+ i r channel positive analog video input rin1 - i r channel negativ e analog video input hsynci i vga port horizontal sync input with schmitt trigger vsynci i vga port vertical sync input with schmitt trigger graphic tmds interface pin type definition rx2+ i tmds input channel 2+ rx2 - i tmds input channel 2 - rx1+ i tmds input channel 1+ rx1 - i tmds input channel 1 - rx0+ i tmds input channel 0+ rx0 - i tmds input channel 0 - rxc+ i tmds input clock pair rxc - i tmds input clock pair rext i external termination resistor avcc power tmds analog vcc must be set to 3. 3v. agnd power tmds analog gnd. pvcc power tmds pll analog vcc must be set to 3.3v. pgnd power tmds pll analog gnd. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 16 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. lvds panel interface pin type definition video itu - r bt656 interface pin type definition v0~v7 o video port data[7:0] input vclk o video port clock power pin pin typ e definition cvdd power core logic power supply (1.8v) pin. external capacitor (0.1uf) connected is recommended. cgnd /dvdd power core logic ground /display digital power supply pll_vdd power core logic power supply (1.8v) pin for pll. external capacito r (0.1uf) connected is recommended. pll_gnd power core logic ground pin for pll. avcc power tmds analog vcc must be set to 3.3v. agnd power tmds analog gnd. pvcc power tmds pll analog vcc must be set to 3.3v. pgnd power tmds pll analog gnd. adc_vaa power adc analog power supply adc_gnda power adc analog ground t0m lvdso negative lvds differential data output of channel 0 t0p lvdso positive l vds differential data output of channel 0 t1m lvdso negative lvds differential data output of channel 1 t1p lvdso positive lvds differential data output of channel 1 t2m lvdso negative lvds differential data output of channel 2 t2p lvdso positive lvds differential data output of channel 2 tclk1m lvdso negative lvds differential clock 1 output tclk1p lvdso positive lvds differential clock 1 output t3m lvdso negative lvds differential data output of channel 3 t3p lvdso positive lvds differential data output of channel 3 t4m lvdso negative lvds differential data output of channel 4 t4p lvdso positive lvds differential data output of channel 4 t5m lvdso negative lvds differential data output of channel 5 t5p lvdso positive lvds differential data outp ut of channel 5 t6m lvdso negative lvds differential data output of channel 6 t6p lvdso positive lvds differential data output of channel 6 tclk2m lvdso negative lvds differential clock 2 output tclk2p lvdso positive lvds differential clock 2 output t 7m lvdso negative lvds differential data output of channel 7 t7p lvdso positive lvds differential data output of channel 7 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 17 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6. functional description 6.1. power control nt68667 supports the whole chip power down functio n except mcu logic and sync - processor (include sog slicer, and tmds sync detect ) when h/w reset . f igure 6.1 - 1 power control block 6.2. analog to digital converter (adc) nt68667 provides a clock - recovery circuit and an analog - to - digital converter to effectively save the cost of needing external expensive adc a nd pll. the gain and offset circuit is used to adjust the gain (contrast) of input video amplitude and shift the dc offset voltage (brightness). the clock - recovery circuit consisting of a high - speed phase lock loop (pll) is used to generate the clock to sa mple analog rgb data. this circuit is locked to the hsync of the incoming video signal. the analog - to - digital converter (adc) transfers the input analog rgb video to digital output data with each color 8 - bit resolution. gain and offset control rin/gin/bin are high - impedance input pins that accept the red, green, and blue channel graphics signals. they accommodate input signals ranging from 0.55v to 0.9v full scale. signals should be ac - couple to these pins. due to ac coupling, clamping pulse is needed to d efine the time during which the input signal is clamped to ground, establishing a black reference. typically the clamping pulse is defined during the back porch period of the graphics signal. nt68667 generates the clamping pulse internally and the position and duration are programmable. the simpler clamp - timing generator clamping pulse - starting position and pulse width is defined in 0x021[7:0] and 0x022[7:0]. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 18 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. nt68667 has three independent variable gain amplifiers for each channel with input signal range f rom 0.55v to 0.9v p - p , the full - scale range is set in three 9 - bit registers. nt68667 offset control shifts the entire input range, resulting in a change in image brightness. the three independent variable 8 - bit registers provide independent settings for e ach channel. clamp pulse generator this block circuit called clamp pulse generator generates clamp pulse to adc. there are two input trigger sources of the clamp generator, one is signal hin from separator and another is row hs from the hsynci0 / hsynci1. the polarity and the trigger edge of the clamp can be selected by using bit clmp_pol and bit clmp_edg respectively. the trigger delay of the clamp is waiting clmp_beg [5:0] x refclk time. the pulse width of the clamp output may be selected by clmp_wid [5: 0]. ? clamp pulse timing t p w _clmp clamp clmp_edg=1 clmp_pol=1 clamp clmp_edg=0 clmp_pol=1 clamp clmp_edg=1 clmp_pol=0 clamp clmp_edg=0 clmp_pol=0 trailing edge leading edge hsynci / h in positive polarity hsynci / h in negative polarity t d_clmp clamp pulse timing figure 6.2 - 1 clamp pulse timing coast this function is used to cause the pixel clock generator to stop synchronizing with hsync and continues producing a clock at i ts current frequency and phase. this is useful when processing composite sync that fails to produce horizontal sync pulses when in the vertical interval. 6.3. dvi receiver the dvi receiver uses panel link digital technology to support input ranging from vga t o uxga (25 - 165 mhz), which is ideal for desktop and specialty applications. 6.4. graphic port capture interface the function of graphic port capture interface is to provide two interfaces between nt68667 and external input devices. it can process non - interlaced and interlaced rgb graphic input, and dvi input. user should select the video input source from graphic port (vga or dvi) and the polarity of external control signal, and then program the h/v captures size registers to indicate the display area. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 19 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6.5. video po rt capture interface the function of video port capture interface is to provide digital yuv interface between nt68667 and video decoder. it can process non - interlaced and interlaced digital yuv video itu bt656 input. it includes color space conversion for yuv to rgb color space conversion. 6.6. auto tune the auto tune function consists of auto gain, auto position, and auto phase. with such auto adjustment support it is possible to measure the correct phase, frequency, gain, and offset of adc. the horizontal and vertical back porches of input image and the horizontal and vertical active regions can also be measured. 6.7. video processor video processor consists of interpolation control, rgb gain control, rgb offset control, hue and saturation control, dithering contro l, gamma correction control and srgb support. nt68667 enhanced interpolation method makes the zoomed display image look more smooth and comfortable. user can adjust the rgb gain (contrast) and rgb offset (brightness) by the registers in the adcpll block, o r registers in the video processor block. but for yuv video input, it is suitable to adjust contrast and brightness at here. in addition, it supports all yuv color controls including brightness, contrast, hue and saturation. dithering function can provide 16.7 million colors space for 6 - bit/color panel. it is recommended to open the dithering function while a 6 - bit panel is used. nt68667 provide independently horizontal and vertical zoom scaler with adjustable zoom factor from 1/4x to 4x. each of the zoom s caler uses variable sharpness filter to provide high quality scaling of real - time video and still graphic images. interpolation 1. flexible sharpness filter nt68667 include flexible sharpness filter for horizontal and vertical sharpness adjusting. users c an use them by register programming. 2. vertical spatial interpolation when interlaced video or images are applied, the nt68667 vertical scaling engines will de - interlace the input fields spatially and reposition them to align the display?s line map. 3. ad vanced filter with the aid of two selectable advanced filters when zooming up horizontally, nt68667 provides the most undistorted image from the original one. srgb support srgb is a standard for color exchange proposed by microsoft and hp. the srgb contro ls can be used to make lcd monitors srgb compliant. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b g r offset offset offset b g r c b a c b a c b a b g r srgb srgb srgb srgb srgb srgb 2 2 2 1 1 1 0 0 0 ' ' ' ----------------------------------- [1] gamma correction ? provides 10 - bit gamma correction function ? f/w needs to define total 256 end - point value in advance free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 20 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0 256 512 768 1024 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 gamma = 1.0 gamma = 2.2 gamma = 1/2.2 figure 6.7 - 1 gamma correction curve index address gamma table value 0 lsb0 (2 bits)+msb0 (8 bits) 1 lsb1+msb1 2 lsb2+msb2 ?. ?. 254 lsb254+msb254 255 lsb255+msb255 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 21 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6.8. sync processor the nt68667 has a sync processor block providing the capability of measuring the horizontal and vertical timing parameters of the input video source. this information may be used to determine the video format and to detect a change in the input timing. it is also cap able of detecting the field type of interlaced formats. hsync /vsync frequency and polarity detection gi_hcnt, the 13 bits hsync period counter counts the time of 32xhsync period, then loads the result into the gi_hcnt latch. the output value will be [((r efclk / 4 x 32)/h f req)], updated once per vsync/cvsync period when vsync/cvsync is present or continuously updated when vsync/cvsync is non - present. gi_vcnt, the 13 bits vsync period counter counts the time between two vsync pulses, then loads the result i nto the gi_vcnt latch. the output value will be [(refclk/(256 x vfreq))], updated every vsync/cvsync period. an extra overflow bit indicates the condition of h/v counter overflow. the polarity functions detect the input hsync/vsync high and low pulse duty cycle. if the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. the int_hpol interrupt is set when the gi_hpol value changes. the int_vpol interrupt is set when the gi_vp ol value changes. h/v present check the hsync present function checks the input hsynci pulse, gi_hpre flag is set when hsynci is over hsync present high counter threshold (hpre_thr_hi) or cleared when hsync is under hsync present low counter threshold (hp re_thr_lo). the vsync present function checks the input vsynci pulse, the gi_vpre flag is set when vsynci is over vsync present high counter threshold (vpre_thr_hi) or cleared when vsync is under vsync present low counter threshold (vpre_thr_lo). the int_h pre interrupt is set when the gi_hpre value changes. the int_vpre interrupt is set when the gi_vpre /gi_cspre value change. timing change detection the int_vfreq/int_hfreq interrupt is set when gi_vcnt / gi_hcnt value changes or overflows. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 22 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. extract vsync f rom composite/sog signal t widen(vso) t extract(vso) = fixed vsync hsync single serrated xored ored double serrated + equal. extracted vso h/v sync timing pre-equal. pulses post-equal. pulses serration pulses inserted pulses t pw(insert) vertical blanking interval t pw(insert) inserted pulses extracted hso from sogi / hsynci extracted hso from sog / hsynci internal coast internal coast pre_coast = 3 pos_coast = 3 figure 6.8 - 1 h/v timing internal odd/even field detection included in the sync detector is circuitry to determine which field is currently being input for interlace d input. to determine the field based on position of vsync relative to hsync, the gi_fld_winbeg (3:0) and gi_fld_winend (3:0) registers are used for graphic port and the vi_fld_winbeg (3:0) and vi_fld_winend (3:0) registers are used for video port. the nt6 8667 divides each horizontal line into 16 equal intervals. the fld_winbeg bits are used to specify at which 1/16 th of a line to start looking for the leading edge of vsync. the fld_winend bits are used to specify at which 1/16 th of a line to stop looking. if the leading edge of vsync occurs between during or after the 1/16 th line specified by fld_winbeg, but no later than the 1/16 th line specified by fld_winend, the current field is marked as odd. otherwise, a leading edge transition outside these boundarie s will cause the current field to be marked even. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 23 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. fld_winend fld_winbeg odd even hsync vsync ifield fld_winend fld_winbeg vsync ifield even odd hsync interlaced field detection window figure 6.8 - 2 interlaced field detection window free run timing generator this block can generate various free - running outputs to satisfy v arious application requirements. the pulse width of the h free output is fixed 15 x refclk and the v free is 3 hfrees. user can properly set the content of hso free run divider, hfree_div, to get the need frequency of the hso, and set the content vso free ru n divider, vfree_div, to get the frequency of the vso. details refer to the descriptions of the free - run registers hfree_div and vfree_div. refer to the descriptions of the register for details to get user?s need frequencies. users can disable h/v free run output by clearing gi_hrun_en /gi_vrun_en. sync on green slicer this function is provided to assist with processing signals with embedded sync, typically on the gin channel. the circuit sliced the signals that with embedded sync, and apply to sync separ ator for extracting hsync and vsync. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 24 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6.9. osd function osd font?s attribute and code format, palette format definition: osd palette format 15:11 10:5 4:0 r g b osd code format 7:0 font index osd attribute format 15:8 7:4 3:2 1 0 pa_index [7:0] bg_i ndex [3:0] ca_bit mix blink figure 6.9 - 1 ? blink : 0 ? no blinking 1 ? blinking (all color is blinking except background color) ? mix : 0 ? normal 1 ? translucent ((1 - tp_level _one ) display + (tp_lev el _one ) osd_bg) ? ca_bit [1:0] : character attribute bits/pixel number 00: one bit/pixel color font (0 - 255 font index) 01: one bit/pixel color font (256 - 511 font index) 10: two bits/pixel color font 11: three/ four bits/pixel color font ? pa_index [7:0] / bg_in dex [3:0]: attribute color palette index case a: pixel is outside an active window one bit per pixel. foreground ?1? pixel [7:0] <= pa_index [7:0] + 1 background ?0? pixel [7:0] <= bg_index [3:0] two bit per pixel. foreground ?11? pixel [7:0] <= pa_in dex [7:0] + ?11? foreground ?10? pixel [7:0] <= pa_index [7:0] + ?10? foreground ?01? pixel [7:0] <= pa_index [7:0] + ?01? background ?00? pixel [7:0] <= bg_index [3:0] four bit per pixel. foreground ?1111? pixel [7:0] <= pa_index [7:0] + ?1111? foreg round ?1110? pixel [7:0] <= pa_index [7:0] + ?1110? foreground ?1101? pixel [7:0] <= pa_index [7:0] + ?1101? foreground ?1100? pixel [7:0] <= pa_index [7:0] + ?1100? foreground ?1011? pixel [7:0] <= pa_index [7:0] + ?1011? foreground ?1010? pixel [7:0] <= pa_index [7:0] + ?1010? foreground ?1001? pixel [7:0] <= pa_index [7:0] + ?1001? foreground ?1000? pixel [7:0] <= pa_index [7:0] + ?1000? foreground ?0111? pixel [7:0] <= pa_index [7:0] + ?0111? free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 25 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. foreground ?0110? pixel [7:0] <= pa_index [7:0] + ?0 110? foreground ?0101? pixel [7:0] <= pa_index [7:0] + ?0101? foreground ?0100? pixel [7:0] <= pa_index [7:0] + ?0100? foreground ?0011? pixel [7:0] <= pa_index [7:0] + ?0011? foreground ?0010? pixel [7:0] <= pa_index [7:0] + ?0010? foreground ?0001? p ixel [7:0] <= pa_index [7:0] + ?0001? note: if bg_index [3:0] = ?0000?, indicates that this background color is transparent if bg_index [3:0] = ?0001? , background <= pa_index [7:0] case b: pixel is inside an active window one bit per pixel. foreground ?1? pixel [7:0] <= pa_index [7:0] + ?1? background ?0? pixel [7:0] <= winx_attr [7:0] two bit per pixel. foreground ?11? pixel [7:0] <= pa_index [7:0] + ?11? foreground ?10? pixel [7:0] <= pa_index [7:0] + ?10? foreground ?01? pixel [7:0] <= pa_index [7:0] + ?01? background ?00? pixel [7:0] <= winx_attr [7:0] four bit per pixel. foreground ?1111? pixel [7:0] <= pa_index [7:0] + ?1111? foreground ?1110? pixel [7:0] <= pa_index [7:0] + ?1110? foreground ?1101? pixel [7:0] <= pa_index [7:0] + ?1101? foreground ?1100? pixel [7:0] <= pa_index [7:0] + ?1100? foreground ?1011? pixel [7:0] <= pa_index [7:0] + ?1011? foreground ?1010? pixel [7:0] <= pa_index [7:0] + ?1010? foreground ?1001? pixel [7:0] <= pa_index [7:0] + ?1001? foreground ?1000? pixel [7:0] <= pa_index [7:0] + ?1000? foreground ?0111? pixel [7:0] <= pa_index [7:0] + ?0111? foreground ?0110? pixel [7:0] <= pa_index [7:0] + ?0110? foreground ?0101? pixel [7:0] <= pa_index [7:0] + ?0101? foreground ?0100? pixel [7:0] <= pa_index [7:0 ] + ?0100? foreground ?0011? pixel [7:0] <= pa_index [7:0] + ?0011? foreground ?0010? pixel [7:0] <= pa_index [7:0] + ?0010? foreground ?0001? pixel [7:0] <= pa_index [7:0] + ?0001? background ?0000? pixel [7:0] <= winx_attr [7:0] free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 26 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. palette address and map figure 6.9 - 2 palette palette n palette address bits [15:11] bits [10:5] bits [4:0] palette 0 0 (0x00h) r0 [4:0] g0 [5:0] b0 [4:0] palette 1 1 (0x01h) r1 [4:0] g1 [5:0] b1 [4:0] palette 2 2 (0x02h) r 2 [4:0] g2 [5:0] b2 [4:0] ? ? palette 15 15 (0x0fh) r15 [4:0] g15 [5:0] b15 [4:0] palette 16 16 (0x04h) r16 [4:0] g16 [5:0] b16 [4:0] palette 17 17 (0x05h) r17 [4:0] g17 [5:0] b17 [4:0] ? ? palette 254 254 (0xfeh) r254 [4:0] g254 [5:0] b254 [4: 0] palette 255 255 (0xffh) r255 [4:0] g255 [5:0] b255 [4:0] figure 6.9 - 3 palette address and map p255 p254 p2 53 p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p 18 p17 p16 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 27 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. osd character map figure 6.9 - 4 osd character map osd font definitions one bit per pixel one bit per pixel font definitions are arranged in color character font sram memory on a 12 - bit by 18 - address grid. the one bit per pixel osd programmable font start address is specified in register 0x089 ~ 0x088. odd font def initions are stored in sram bits [11:0], and even font definitions are stored in sram bits [23:12]. figure 6.9 - 5 one bit per pixel font font bitmask 000000000000 000000000000 000000000000 000011111000 000111111100 001100001100 001100001100 0000000 11000 000000110000 000001100000 000011000000 000110000000 001100000000 001111111100 001111111100 000000000000 000000000000 000000000000 1 0 font_x = 12 pixels font_y = 18 lines address 1: character attribute for character upper - left osd_hw osd_vh address 25: character attribute for character upper - right free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 28 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. tw o bit per pixel two bits per pixel font definitions are arranged in color character font sram memory on a 24 - bit by 18 addresses. the two bit per pixel osd programmable font start address is specified in register 0x08b ~ 0x08a. font definitions are stored in sram bits [23:0]. figure 6.9 - 6 two bit per pixel font t hree bit per pixel three bits per pixel font definitions are arranged in color character font sram memory on a 24 - bit by 36 addresses. the four bit per pixel osd programmable font start address is specified in register 0x08d ~ 0x08c. each pixel row of a font contains up 12 pixels, with the font row broken up across two consecutive color chara cter font sram memory addresses. font bit mask 000000000000000000000000 000000000000000000000000 000000000010101010000000 000000000101010101100000 000000010101010101011000 0000010100000 00001011000 000001010000000001011000 000000000000000101100000 000000000000010110000000 000000000001011000000000 000000000101100000000000 000000010110000000000000 000001011010101010101000 000001010101010101011000 000001010101010101011000 0000000000000000000 111111111111111111111111 000000000000000000000000 01 00 10 11 font_x = 12 pixels font_y = 18 lines font bitmask 01234567 0000 0000000000000 00000111 1000 0000 44444 100 000 4444444 10 00 44 0000 44 10 00 44 0000 44 10 0000000 44 100 000000 44 1000 00000 44 10000 0000 44 100000 000 44 1000000 00 44 11111110 00 44444444 10 00 444444444 10 000000000000 555555555555 000000000000 0 1 2 3 4 5 6 7 font_x = 12 pixels font_y = 18 lines free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 29 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. figure 6.9 - 7 three bit per pixel font fo ur bit per pixel four bits per pixel font definitions are arranged in color character font sram memory on a 24 - bit by 36 addresses. the four bit per pixel osd programmable font start address is specified in register 0x08d ~ 0x08c. each pixel row of a font contains up 12 pixels, with the font row broken up across two consecutive color character font sram memory addresses. figure 6.9 - 8 four bit per pixel font font bitmask 0123456789ab cdef99999999 000001111000 0000eeeee100 000eeeeeee10 00ee0000ee10 00ee0000ee10 0000000ee100 000000ee1000 00000ee10000 0000ee100000 000ee1000000 00ee11111110 00eeeeeeee10 00eeeeeeeee10 000000000000 555555555555 000000000000 0 1 2 3 4 5 6 7 8 9 a b c d e f font_x = 12 pixels font_y = 18 lines font bit mask 000000000000000000000000 000000000000000000000000 000000000010101010000000 0000000001010101011000 00 000000010101010101011000 000001010000000001011000 000001010000000001011000 000000000000000101100000 000000000000010110000000 000000000001011000000000 000000000101100000000000 000000010110000000000000 000001011010101010101000 000001010101010101011000 000 001010101010101011000 0000000000000000000 111111111111111111111111 000000000000000000000000 01 00 10 11 font_x = 12 pixels font_y = 18 lines free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 30 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. osd color character font sram memory arrangement m ap: a single ported sram (4096 - words 24 - bits) is used for storing character attribute, code index, and programmable fonts. the following example illustrates the contents of sram memory for a sample osd. the osd is three rows by four columns. note: tha t the osd frame sram and font sram share the same on color character font sram memory. thus, the size of the memory map can be traded off against the number of different memory definitions. in particular, the size of the osd frame and the number of font da ta must fit in the color character font sram memory. that is, the following inequality must be satisfied. (osd_hw+1)(osd_vh+1) + 18celing (number of 1 - bit per pixel fonts / 9) 9 + 218celing (number of 2 - bit pixel fonts / 9) 9 + 3/ 418celing (num ber of 4 - b it pixel fonts / 9) 9 <= 5120 the programmable font start address setting: osd one bit font address (font1b_addr) = (osd_hw+1)(osd_vh+1) osd two bits font address (font2b_addr) = osd one bit font address (font1b_addr) + (number of 1 - bit per pixel fonts) (1218/24) osd three/four bits font address (font3b_addr/ font4b_addr) = osd two bit font address (font2b_addr) + (number of 2 - bit per pixel fonts) (21218/24) note: the following inequality must be satisfied mod (number of 1 - bit pixel fo nts / 9) = 0 mod (number of 2 - bit pixel fonts / 9) = 0 mod (number of 4 - bit pixel fonts / 9) = 0 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 31 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. osd frame definition: figure 6.9 - 9 osd active frame and windows osd_hs : osd frame horizontal start (0 ? 204 7 pixels) osd_hw : osd frame horizontal width (1 ? 64 chars) osd_vs : osd frame vertical start (0 ? 2047 pixels) osd_vh : osd frame vertical height (1 ? 32 chars) win_hs : osd window horizontal start (1 ? 64 chars) win_he : osd window horizontal end (1 ? 6 4 chars) win_vs : osd window vertical start (1 ? 32 chars) win_ve : osd window vertical end (1 ? 32 chars) font_x : font x size (12/10 pixels) font_y : font y size (16/18 lines) active display screen osd_hs osd_hw d osd_vh osd_vs font_y font_x n o v a t ek osd ( win_he, win_ve ) ( win_hs, win_vs ) osd window 1 - 4 frame origin point ( 0, 0 ) free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 32 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6.10. dpll clock control nt68667 display pll (bandwidth 1 70 mhz) for display timing generator. formula: fout = (reference - freq ddds_ratio [21:0]) / 2 17 fref = 12.000 mhz note: the value (reference - freq ddds_ratio [21:0] / 2 17 ) must be large to 100 mhz free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 33 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6.11. display interface nt68667 display interface supports single (24 - bit) or dua l (48 - bit) pixel out format, and supports the 6 - bit/color or 8 - bit/color lcd panel. built in internal pll locking to the reference clock generates all of the display timing to various lcd panels. nt68667 also provides the programmable display driving capa city to reduce emi influence as well as programmable clock delay to compensate clock skew. active window dh_hs_wid dh_bg_beg dh_bg_wid de display background window dh_act_beg dv_vs_wid dv_act_beg dv_act_len dv_bg_len dv_bg_beg dh_total display timing control dh_act_wid dv_total figure 6.11 - 1 display timing control 6.11.1. scaler display data disp_clk disp_de ba, ga, ra[0:7] bb, gb, rb[0:7] data 0 data 1 data 2 data 3 data 4 figure 6.11 - 2 single pixel width display data free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 34 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. disp_clk disp_de ba, ga, ra[0:7] bb, gb, rb[0:7] data 0 data 2 data 4 data 6 data 8 data 1 data 3 data 5 data 7 data 9 figure 6.11 - 3 double pixel width display data 6.11.2. single/dual pixel lvds transmitter the nt68667 transmitter i s de - signed to support single or dual pixel data transmission between scaler and flat panel display up to w sxga resolutions. for single pixel mode, the transmitter converts 24 bits (si ngle pixel 24 - bit color) data into 4 lvds (low voltage differential sign aling) data str eams. for dual pixel mode, the transmitter converts 48 bits (d ual pixel 24 - bit color) data into 8 lvds (low voltage differential signaling) data streams control signals (vsync, hsync, de and two user - defined signals) are sent during blanking intervals. the lvds transmitter can support the following: 1. single or double pixel mode 2. 24/48 - bit panel mapping to the lvds channels 3. 18/36 - bit panel mapping to the lvds channels 4. programmable even/odd lvds swapping 5. programmable channel swapping (the clocks are fixed) 6. support up to ws xga 75 hz output panel data mappings dual pixel mode (when dp_bit_shf = 0) channel 0 / channel 4 r0, r1, r2, r3, r4, r5, g0 channel 1 / channel 5 g1, g2, g3, g4, g5, b0, b1 channel 2 / channel 6 b2, b3, b4, b5, hs, vs, de ch annel 3 / channel 7 r6, r7, g6, g7, b6, b7, rsvd lvds output d7 d6 d4 d3 d2 d1 d0 lvds channel 0 (t0) data order ga0 ra5 ra4 ra3 ra2 ra1 ra0 lvds output d18 d15 d14 d13 d12 d9 d8 lvds channel 1 (t1) data order ba1 ba0 ga5 ga4 ga3 ga2 ga1 lvds output d26 d25 d24 d22 d21 d20 d19 lvds channe l 2 (t2) data order de vs hs ba5 ba4 ba3 ba2 lvds output d23 d17 d16 d11 d10 d5 d27 lvds channel 3 (t3) data order rsvd ba7 ba6 ga7 ga6 ra7 ra6 lvds output d7 d6 d4 d3 d2 d1 d0 lvds channel 4 (t4) data order gb0 rb5 rb4 rb3 rb2 rb1 rb0 lvds output d18 d15 d14 d13 d12 d9 d8 lvds channel 5 (t5) data order bb1 bb0 gb5 gb4 gb3 gb2 gb1 lvds channel 6 (t6) lvds output d26 d25 d24 d22 d21 d20 d19 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 35 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. data order de na na bb5 bb4 bb3 bb2 lvds out put d23 d17 d16 d11 d10 d5 d27 lvds channel 7 (t7) data order na bb7 bb6 gb7 gb6 rb7 rb6 dual pixel mode (when dp_bit_shf = 1) channel 0 / channel 4 r2, r3, r4, r5, r6, r7, g2 channel 1 / channel 5 g3, g4, g5, g6, g7, b2, b3 channel 2 / channel 6 b4, b5, b6, b7, hs, vs , de channel 3 / channel 7 r0, r1, g0, g1, b0, b1, rsvd lvds output d7 d6 d4 d3 d2 d1 d0 lvds channel 0 (t0) data order ga2 ra7 ra6 ra5 ra4 ra3 ra2 lvds output d18 d15 d14 d13 d12 d9 d8 lvds channel 1 (t1) data order ba3 ba2 ga7 ga6 ga5 ga4 ga3 lvds output d26 d25 d24 d22 d21 d20 d19 lvd s channel 2 (t2) data order de vs hs ba7 ba6 ba5 ba4 lvds output d23 d17 d16 d11 d10 d5 d27 lvds channel 3 (t3) data order rsvd ba1 ba0 ga1 ga0 ra1 ra0 lvds output d7 d6 d4 d3 d2 d1 d0 lvds channel 4 (t4) dat a order gb2 rb7 rb6 rb5 rb4 rb3 rb2 lvds output d18 d15 d14 d13 d12 d9 d8 lvds channel 5 (t5) data order bb3 bb2 gb7 gb6 gb5 gb4 gb3 lvds output d26 d25 d24 d22 d21 d20 d19 lvds channel 6 (t6) data order de na na bb7 bb6 bb5 bb4 lvds output d23 d17 d16 d11 d10 d5 d27 lvds channel 7 (t7) data order na bb1 bb0 gb1 gb0 rb1 rb0 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 36 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6.12. miscellaneous 6.12.1. pwm output there are two pulse width modulation signal pins available for controlling the lcd back light or audio volume, pwma and pwmb. the duty cycle and fr equency of these signals is programmable. pwm_hcnt pwm_lcnt fref figure 6.12 - 1 pulse width modulation signal (pwm) when clock source select from reference clock ) pwm_div (pwm_div f f refclk pwm_clk 2 1 u when clock source select from display hsync ) pwm_div (pwm_div f f hs disp pwm_clk 2 1 _ u pwm pwm_clk pwm pwm_clk pwm_clk pwm f f duty lcnt pwm f f duty hcnt pwm pwm_lcnt pwm_hcnt hcnt pwm duty pwm_lcnt) (pwm_hcnt f f u u ) 1 ( _ _ ) ( _ pwm_hcnt pwm_lcnt pwm output 0 0~255 dc ?0? 1~255 0 dc ?1? 1~255 1~255 pwm pulse free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 37 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6.13. mcu interface 6.13.1. irqn interrupt sources nt68667 provides an internal interrupt request output irqn to internal mcu . the following figure shows the detail structure of the irqn sources. flags clear flags or enables irqn irqn interrupt source int_vfreq edge dectect detect rising edge interrupt control edge dectect edge dectect edge dectect edge dectect edge dectect edge dectect edge dectect int_hfreq int_vpol int_hpol int_vedge int_hedge int_ispre int_cspre int_vfreq int_hfreq int_vpol int_hpol int_vedge int_hedge int_ispre int_cspre edge dectect edge dectect int_vpre int_hpre int_hpre int_vpre int_vfreq_en int_hfreq_en int_vpol_en int_hpol_en int_vedge_en int_hedge_en int_ispre_en int_cspre_en int_hpre_en int_vpre_en edge dectect edge dectect int_ffov int_ffun int_ffuv int_ffov int_ffuv_en int_ffov_en edge dectect int_dvipre int_dvipre int_dvipre_en figure 6.13 - 1 irqn interrupt block diagram inthv_irq meaning action int_vfreq vsync frequency change it will be activated when the i nput frequency of vsync changes. int_hfreq hsync frequency change it will be activated when the input frequency of hsync changes. int_vpol v - polarity change int it will be activated when the input polarity of vsync changes. int_hpol h - polarity change in t it will be activated when the input polarity of hsync changes. int_vedge vsync edge int it will be activated when the vsync rising edge is occur. int_hedge hsync edge int it will be activated when the hsync rising edge is occur. int_ispre interlaced s ync int it will be activated when the interlaced sync is present. int_ cspre composite sync int it will be activated when the composite sync is present. int_vpre vsync present int it will be activated when the vsync is present. int_hpre hsync present in t it will be activated when the hsync is present. int_dvipre dvi sync present int it will be activated when the dvi sync is present. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 38 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. int_ffov fifo overflow int it will be activated when the fifo is overflow int_ ffuv fifo underflow int it will be activa ted when the fifo is underflow int_upd_ddc0 ddc0 updated int it will be activated when ddc0 ram - buffer contents updated. int_ upd_ddc1 ddc1 updated int it will be activated when ddc1 ram - buffer contents updated. table 6.13 - 1 irqn interrupt 6.14. 8031 on - chip microcontroller reference nt68667 mcu spec. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 39 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7. electrical specifications absolute m aximum r atings 3.3v supply voltage range, v 3.3 (see note1) ?????????????? . - .. 0.3v to 4v output voltage range, v o?.. ??????.????? ???????.??? - 0.3v to v 33 +0.3v input voltage range (5v tolerant), v i ?????????.????..???? - 0.3v to v 5v +0.3v electrostatic discharge, v esd ????????.????..???????? . ? 2.0 k v esd mm ???????????????????????????? . ? 2 00v ( class 2 ) latch up ?????????????????????????? ?? . . ? 2 00ma ( class 3 ) msl ?????????????????????????????? ...class 3 ambient operating temperature, t a ????????????????.?... . 0 ? c to 70 ? c lead temperature 1, 6 mm (1/16 inch) from case for 10 seconds????? ?? . 260 ? c junction t emperature?????????????????????.?? .. . 150 ? c surface temperature.................................................................................................125 ? c storage temperature range, tstg?????????????????..? ? ... - 40 ? c to 125 ? c storage humidity??????????.??..?????????..???..< 60% hr s torage life (storage temperature < 30 : )????????????? ? ? 1 year ? stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. ? note1: includes pins adc_vaa, avcc, pvcc, dvdd. ? note2: includes pins cvdd, pll_vdd 7.1. dc electrical characteristics (t a = 25 ? c, oscillator freq. = 12.000mhz, unless otherwise specified) symbol parameter min. typ. max. unit conditions power requirements v cvdd 1.8 v digital power supply 1. 6 1.8 2.0 v cvdd v pll pll power supply 1. 6 1.8 2.0 v pll_vdd v adc r/g/b channel adc analog power supply 3. 15 3.3 3.47 v adc_vaa, v tmdsa tmds analog power supply 3.15 3.3 3.47 v av c c v tmdsp tmds pll power supply 3.15 3.3 3.47 v pvcc v ddd display interface power s upply 3.15 3.3 3.47 v dvdd i adc adc power supply current 1 50 ma i tmds tmds power supply current 1 60 ma i dd33 3 .3 v operating current 2 00 ma except adc, tmds i ddpd33 3.3 v power down current 2 0 ma inculde adc,tmds.dvdd digital outputs v oh o utput high voltage 2.0 v dd v in_hso, in_vso free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 40 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. v ol output low voltage gnd 0.8 v v oh output high voltage for open drain type 5 v pwm[ 6 : 9 ],pwm a, pwmb , ddc_scl[1:0], ddc_scl[1:0], pc0,pc1 i oz tri - state leakage current - 25 25 ua i oh output high current - 16 - 2 ma (v oh = 2.5v) disp _de, disp_vs, disp_hs, disp_clk gpo[8:1] i ol output low current 2 16 ma (v ol = 0.4v) disp_de, disp_vs, disp_hs, disp_clk gpo[8:1] lvds outputs lv od l differential steady - state output voltage magnitude 240 mv iv od i change in the steady - state differential output voltage magnitude between opposite binary states 35 mv r l = 100 ? , see figure 7.1.1 v oc(ss) steady - state common - mode output voltage 1.125 1.475 v v oc(pp) peak - to - peak common - mode output vo l t a g e 80 150 mv see figure 7.1.1 24 ma v o(tp) = 0 i os short - circuit output current 12 ma v od = 0 i oz output tri - state current 1 a v o = 0 to vcc analog input v iamin minimum input voltage range 0.55 v p - p v iamax maximum input voltage range 0.9 v p - p v iamax dvi input v id differential input voltage 150 1200 mv see figure 7.1.3 v icom input common mode voltage av c c - 300m av c c - 37mv mv see figure 7.1.3 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 41 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. v v btd behavior when transmitter is disabled av c c - 10mv av c c + 10mv mv see figure 7.1.3 digital input v ih input high voltage 2.0 v dd v v il input low voltage gnd 0.8 v y[7:0], v t+(hsyn c) schmitt trigger positive going threshold voltage for hsync inputs 1.5 1.6 2.2 v hsynci0, hsynci1 v t - (hsyn c) schmitt trigger negative going threshold voltage f or hsync inputs 0.7 1.1 1.4 v hsynci0, hsynci1 v t+(vsyn c) schmitt trigger positive going threshold voltage for vsync inputs 1.8 2.0 v vsynci0, vsynci1 v t - (vsyn c) schmitt trigger negative going threshold voltage for vsync inputs 0.8 1.5 v vsynci0, vsync i1 v ihc clock high voltage 2.0 v dd v v ilc clock low voltage gnd 0.4 v yuv_clk, i ih input high current - 25 25 a (v ih = 2.5v) i il input low current - 25 25 a (v il = 0.4v) free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 42 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. (a) schematic v od(l) 100% 80% 0v 20% 0% t r t f v oc(ss) v oc(ss) 0v v oc(pp) v od(h) 7 waveforms figure 7.1 - 1 test load and voltage definitions for lvds outputs rstn all output internal register initial period programmed timing power - up sequence 3 . 0 v 2 . 5 v > 0 . 5 ms vdd figure 7.1 - 2 power - up sequence v od vo c cl = 10 pf max (2 places) tp tm 49.9 : 1% (2 places) free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 43 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. v id v icom avcc rx+ rx- figure 7.1 - 3 dvi single - ended differential signal free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 44 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7.2. ac electrical characteristics (vdd=3.3v, ta=25 ? c, oscillator freq.= 12 mhz, unless otherwise specified) adcpll phase - locked loop symbol parameter conditions min typ max unit j pll short term jitter fclkout= 188 mhz - 120 - ps long term jitter fclkout= 188 mhz - 0. 6 - ns dr divider ratio - 2 - 4096 f clkin input hs frequency range - 15 - 110 k h z f or normal type 1 5 - 166 for h type 15 - 188 f clkout output clock frequency range for u type 15 190 m h z t cap pll capture time in start - up conditions - - 5 ms ckout clock duty cycle 165 mhz output 45 50 55 % clamping pul se symbol parameter conditions min typ max unit t delay clamp pulse delay time clamp_beg<5:0>=0x00 - 0 - 4/ckout clamp_beg<5:0>=0x0f - 15 - 4/ckout t width clamp pulse width clamp_wid<5:0>=0x01 - 1 - 4/ckout clamp_wid<5:0>=0x0f - 15 - 4/ckout t co r1 clamp correction time to within 10 mv 100mv black level input variation; clamp capacitor = 4.7nf - - 300 ns t cor2 clamp correction time to less than 1 lsb 100mv black level input variation; clamp capacitor = 4.7nf - - 10 lines analog - to - digital co nverter symbol parameter conditions min typ max unit for normal type 1 5 - 166 for h type 15 188 fs sampling frequency for u type 15 190 m h z g match channel to channel match - - 2 5 % vin(p - p) input signal voltage (peak - peak) corresponding to f ull scale output 0.55 0.7 0.9 v dnl dc differential non linearity from analog input to digital output; ramp input; - 0.5 lsb free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 45 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. inl dc integral non linearity from analog input to digital output; ramp input; - 0.6 lsb enob effective number of bits from analog input to digital output;10khz sine wave input; ramp input - 7 - bits thd input 1v(p - p) and 10mhz - - 1 % no missing codes is guaranteed. signal - to - noise ratio symbol parameter conditions min typ max unit s/n signal - to - noise ratio maximum gain - 45 - db minimum gain - 44 - db tmds receiver tmds receiver symbol parameter conditions min typ max unit f op operating frequency range 25 - 165 mhz t jjt jitter tolerance 2 - - ns t start receiver startup time - - 10 ms t dps intra - pair (+ t o - ) differential input skew 165mhz 1 pixel/clock 250 ps t ccs channel to channel differential input skew 165mhz 1 pixel/clock 5.0 ns c in tmds input pin capacitance - 7 - pf sync processor (oscillator freq.=12mhz) h/v sync processor symbol paramet er conditions min typ max unit f vsync vsync input frequency vsync duty cycle = 40% 15 - 250 hz f vclk vsync input frequency for ddc - 1 mode supply vclk for ddc - 1 mode only - - 25 khz t vpw vsync input pulse width vsync duty cycle < 40% - - 2.5 ms f hsync h sync input frequency hsync duty cycle = 40% 15 - 250 khz t hpw hsync input pulse width hsync duty cycle < 40% - - 8.66 us t hpw(comp) hsync input pulse width hsync duty cycle < 40% - - 8.66 us t httt(comp) horizontal total time 8.66 us free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 46 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. t d 6 t d 5 t d 4 t d 3 t d 1 t d 2 t d 0 t d 7 t d 7 ?? 0.5v 1.4v ?? clkin t d 0 - t d6 v od(l) v od(h) 0.00v tclk or tn clkin (rfb=0) clkin (rfb=1) tclk tn td4 td3 td2 td1 td0 td7 td6 td6+1 td7+1 figure 7.2 - 1 lvds timing definitions ? ? ? ? ? ? ? ? ? ? t en invalid valid clkin tdn pwdn tclk figure 7.2 - 2 lvds enable time waveforms clkin tclk t dis pwdn figure 7.2 - 3 lvds disable time waveforms free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 47 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8. registers mapping block name byte offset adc pll interface page 0 0x000 ~ 0x017 dvi input control 1 0x018 ~ 0x01e graphic port control 0x020 ~ 0x03f video port control 0x040 ~ 0x05f back end image processing 0x060 ~ 0x064 nr control 0x068 ~ 0x06f gpio control 0x070 ~ 0x073 pwm control 0x074 ~ 0x077 ddc control 0x078 ~ 0x07d osd control 0x080 ~ 0x0cf index port access control 0x0e0 ~ 0x0e3 misc. access contr ol 0x0e5 ~ 0x0e6 hs digital pll 0x0d0 ~ 0x0 e f display digital pll & ssc 0x0f0 ~ 0x0f7 power control page 1 0x101 ~ 0x102 auto tune 0x106 ~ 0x12f bright frame display 0x130 ~ 0x13b display general control 0x150 ~ 0x18f sync processor 0x196 ~ 0x1b0 srgb control 0x1d0 ~ 0x1df timing control page 2 0x200 ~ 0x2ff hdcp page 3 0x300 ~ 0x36f dithering control 0x370 ~ 0x371 non - linear scaling adjust 0x380 ~ 0x38b bright frame 0x390 ~ 0x3fe dynamic backlight control page 4 0x 430 ~ 0x 43 f free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 48 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8.1. adc interface 0x000 adcpll control r/w bits name description 7 - 5 reserved 4 hpll_hsync_sel hpll hsync input signal selection 0: hsynci ( from hsynci ) 1: sync_hs ( from sync processor ) 3 hsync_sel hpll hsync input signal selection 0: hsynci ( from hsynci ) 1: sogi 2 - 0 reserved default: 1010 0000b 0x001 red channel gain control r/w bits name description 7 - 0 rgain[8:1] the ragain[7:0] that sets the g ain of the r channel. the adc can accommodate input signals with a full - scale range of between 0.55v and 0.9vp - p. note that increasing rgain results in the picture having less contrast. default: 1000 0000b 0x002 adc common mode r/w bits name description 7 - 0 adc common voltage compensation default: 1000 0000b 0x003 red channel dc shift control r/w bits name description 7 - 0 rcsc [7:0] control the r channel dc shift value to compensate the color excursion. bigger value gives less brightness. default: 1000 0000b 0x004 green channel gain control r/w bits name description 7 - 0 ggain[8:1] the gagain[7:0] that sets the gain of the g channel. the adc can accommodate input signals with a full - scale range of between 0.55v and 0.9vp - p. note that increasing gg ain results in the picture having less contrast. default: 1000 0000b 0x005 adc gain range r/w bits name description 7 - 0 adc gain range compensation default: 0 000 0000b 0x006 green channel dc shift control r/w bits name description 7 - 0 gcsc [7:0] c ontrol the g channel dc shift value to compensate the color excursion. bigger value gives less brightness. default: 1000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 49 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x007 blue channel gain control r/w bits name description 7 - 0 bgain[8:1] the bagain[7:0] that sets the gain of the b channel . the adc can accommodate input signals with a full - scale range of between 0.55v and 0.9vp - p. note that increasing bgain results in the picture having less contrast. default: 1000 0000b 0x008 adc channel and mid clamp control r/w bits name description 7 - 3 reserved 2 channel_sel adc channel 0: disable 1: enable 1 bmid blue clamp select 0: clamp to ground 1: clamp to midscale 0 rmid red clamp select 0: clamp to ground 1: clamp to midscale default: 0000 0100b 0x009 blue channel dc shift control r/w bi ts name description 7 - 0 bcsc[7:0] control the b channel dc shift value to compensate the color excursion. bigger value gives less brightness. default: 1000 0000 0x00a ~ 0x00d : reserved 0x00e adc pll power - up control r/w bits name description 7 - 6 res erved 5 bgain[0] bgain bit 0 4 ggain[0] ggain bit 0 3 rgain[0] rgain bit 0 2 pu_b_adc 1= power - up b channel a2d converter. 1 pu_g_adc 1= power - up g channel a2d converter. 0 pu_r_adc 1= power - up r channel a2d converter. default: 1111 1111b 0x00f : reserved 0x010 analog bandwidth control r/w bits name description 7 - 3 reserved 2 - 1 adc_bw [2:0] analog bandwidth select , bit2 set from 0x1ed.5 011:500m 111:450m 110:400m free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 50 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 101:350m 010:300m 100:250m 001:150m 000:75m 0 reserved default: 0000 0110b 0 x 0 11 : reserved 0x012 sog slicer control r/w bits name description 7 - 3 sog_thr [4:0] the comparator threshold of the sync - on - green slicer to be adjusted. this register adjust it in steps of 10 mv, with the setting 100 mv <= sog_thr <=400 mv 2 en_sog_s licer enable internal sog slicer. 0 = disable 1 = enable 1 - 0 reserved default: 0111 1100b 0x013 white balance control r/w bits name description 7 - 2 reserved 1 - 0 vref[1:0] select the signal source for vga input. when vr1 is selected, the pll will g o into free - run state. 00: vr0. internal zero voltage. 01: add resistor between external rgb and a/d circuit , the adc bandwidth is decided by the two bit and 0x010[2:1] 10: vr1. internal reference voltage 1. (0.7v) 11: normal. from external rgb input pin. default: 0000 0011b 0x014 hsync trigger level control r/w bits name description 7 reserved 6 - 4 hs_thr_h the trigger level threshold of the sync high level to be adjusted. this register adjust it in steps of 100 mv, with the setting 1500 mv <= hs _thr_h <=2000 mv 3 reserved 2 - 0 hs_thr_l the trigger level threshold of the sync low level to be adjusted. this register adjust it in steps of 100 mv, with the setting 950 mv <= hs_thr _l<=1400 mv default: 0000 0000b 0x01 5 v sync trigger level control r/w bits name description 7 vs_schmitt vsi uality triggle 0: disable 1: enable 6 - 4 v s_thr_h the trigger level threshold of the sync high level to be adjusted. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 51 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. this register adjust it in steps of 100 mv, with the setting 1500 mv <= v s_thr_h <=2000 mv 3 reserved 2 - 0 v s_thr_l the trigger level threshold of the sync low level to be adjusted. this register adjust it in steps of 100 mv, with the setting 950 mv <= v s_thr _l<=1400 mv default: 0000 0000b 8.2. dvi input control 1 0x016 dvi clock detection r bi ts name description 7 - 0 dvi_clk dvi clock detection , unit : mhz default: xxxx xxxxb 0x017 : reserved 0x018 dvi control r/w bits name description 7 - 5 reserved 4 for internal circuit dvi control , force to ?0? for normal operate 3 sync_sel sync i s generated from r channel or b channel 0 = from b channel (rx0) 1 = from r channel (rx2) 2 - 0 reserved default: 0000 0000b 0x019 dvi control r/w bits name description 7 - 0 for internal circuit dvi control default: 0000 0000b 0x01a : reserved 0x0 1b dvi control r/w bits name description 7 - 4 reserved 3 - 1 dvi_filt_adj dvi noise filter 000 : weakness 111 : strength 0 dvi_noise_fil noise filter 0: disable 1: enable default: 0000 0000b 0x01c : reserved 0x01d dvi control r/w bits name descri ption 7 - 4 reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 52 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 3 - 0 dvi_pll_bw dvi pll frequence range control 0000 : low frequency 1111 : high frequency default: 0000 0000b 0x01e dvi control r/w bits name description 7 - 0 dvi_eq_data equalizer bias current control default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 53 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8.3. pre - p attern control 0x01f pre - pattern control r/w bits name description 7 pre_patt_en pre - pattern enable. 0 = disable 1 = enable 6 pre_inv pre - pattern data invert 0 = normal 1 = invert the rgb data 5 pre_cbar_en paste a cross bar on the built - in pre - pattern and the bar?s gray level is controlled via cbar_fg[7:0] register (0x15a) 0 = disable 1 = enable 4 pre_patt_bk built - in pre - pattern bank select 0 = bank 0 1 = bank 1 3 - 0 pre_patt_sel [3:0] select built - in pre - pattern type pattern number = 0~7 if pre_pat t_bk = bank 0 0000 = reserved 0001 = dot moir 0010 = vertical line moire (1b1w) 0011 = vertical line moire (2b1w) 0100 = vertical line moire (2b2w) 0101 = 256 v_gray bar 0110 = 256 h_gray bar 0111 = horizontal line moire (1b1w) 1000 = horizontal line moire (2b1w) 1001 = horizontal line moire (2b2w) 1010 = chat pattern 1011 = white pattern 11xx = rectangular pattern, outline width is defined by xx bits. 00 = 1 pixel 01 = 3 pixels 10 = 5 pixels 11 = 7 pixels if patt_bk = bank 1 000 0 = black pattern 0001~1111 = reserved default: 0000 0000b 8.4. graphic port control ? adc/tmds/digital input source selection ? clamp pulse ? interlace decision window ? mask window ? capture window free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 54 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. general control 0x020 graphic port control r/w bits name descri ption 7 gi_vsync_edge mask window and capture vsync referenced edge 0 = leading edge 1 = trailing edge 6 gi_ifld_inv invert the internal field reference signal for data merging priority 0 = normal 1 = invert 5 gi_mkwin_en mask window enable. when g i_mkwin_en =1, gi_hmask_beg, gi_hmask_end, gi_vmask_beg and gi_vmask_end are used to set the window around the hsync and vsync during which the captured data is 0x000 and auto tune is ignored. this filters out noise occurring on the rgb channels around the hsync and vsync pulse. 0 = disable 1 = enable 4 gi_wrap_sel wrap around method select. ( see the figure as below ) 0 = wrap around 1 = wrap black 3 gi_hsync_edge mask window and capture h sync referenced edge. 0 = leading edge 1 = trailing edge 2 gi_inte_en interlaced input enable. when gi_inte_en =1, the field status is reference to internal field detector. 0 = non - interlaced 1 = interlaced 1 gi_src_sel graphic input source select 0 = adc 1 = tmds 0 gi_cap_en graphic input capture enable 0 = disable 1 = enable default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 55 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. h blanking area wrap disable h blanking area wrap enable current h display area next h area current h display area next h area 0x021 clamp pulse begin r/w bits name description 7 clamp_edg clamp pulse reference edge 0 = ghs rising edge 1 = ghs falling edge 6 clamp_pol clamp pulse polarity. 0 = active low 1 = active high 5 - 0 c lamp_beg [5:0] clamp pulse begin. (unit 4xclp_refclk = 4xcapture clock) clamp_beg =5, means waiting 5 x 4clp_refclk after ghs edge to begin the pulse. default: 0000 0000b 0x022 clamp pulse width r/w bits name description 7 clamp_en clamp pulse enable 0 = disable 1 = enable 6 clp_clk_sel clamp pulse reference clock (clp_refclk = capture clock) select 0 = clp_refclk 1 = 2 x clp_refclk 5 - 0 clamp_wid [5:0] clamp pulse width.(unit 4xclp_refclk = capture clock) clamp_wid =5, means pulse width being 6 x 4 clp_refclk wide. default: 0000 1111b 0x023 digital port input control r/w bits name description 7 y p bpr_en y p bpr input enable 6 clamp_source clamp source select. 0 = selects row hs to be used for clamping. 1 = selects sync separated hsync to be us ed for clamping. 5 hs_dejitter_en for tmds input mode, this bit enables/disable the hsync de - jitter free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 56 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. function. 0 = disable 1 = enable 4 dejitter_rst for tmds input mode, de - jitter reset 0 = normal 1 = reset 3 hcap_de_en for tmds input mode, active da ta is enclosed by de signal. hardware can automatically capture the first data and bypass the setting of capture begin registers (0x034~0x035). this bit is effective if dvi_sync_sel=1 (0x196 bit 7). 0 = according to horizontal capture registers 1 = accor ding to de signal 2 reserved 1 dvi_de_auto dvi de auto detection control 0: disable auto de mode 1: enable auto de mode , if input negative de then invert de polarity 0 sync_sel sync processor input path selection 0: graphic 1: video default: 0000 0 000b 0x024 fast mute delay r/w bits name description 7 - 4 fast_mute_delay while input hs mute , delay this programmable delay time , fast mute enable . ?1000? : 1024/ref.clk ?1100? : 512/ref.clk ?1110? : 256/ref.clk 3 - 0 reserved default: 0000 0000b 0x025 adclk delay & invert control r/w bits name description 7 reserved 6 clki_inv internal data latch clock invert 0 = normal 1 = invert 5 - 4 reserved 3 - 0 clki_dly internal data latch clock delay (0.5ns/step) 0~15 step default: 0000 0000b 0x02 6 data delay & swap control r/w bits name description 7 clamp_mask_en clamping pulse mask in v blanking interval 0: disable 1: enable 6 reserved 5 cap_rb_swap capture r/b channel swap 0 = normal 1 = swap free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 57 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 4 - 3 reserved 2 cap_bit_swap capture data b it swap d7 - d0 - > d0 - d7 0 = normal 1 = swap 1 - 0 reserved default: 0000 0000b 0x02 7 ~ 0x29 : reserved mask window define 0x02a horizontal mask window begin r/w bits name description 7 - 0 gi_hmask_beg [7:0] horizontal mask window begin. when gi_mkwin_e n =1, this register sets the number of clocks after the referenced edge (cr:0x020[3]) of the hsync pulse in which the captured data is ?0x00? and the auto - tune starts outside this window. default: 0000 0000b 0x02b horizontal mask window end r/w bits nam e description 7 - 0 gi_hmask_end [7:0] horizontal mask window end. when gi_mkwin_en =1, this register sets the number of clocks before the referenced edge (cr:0x020[3]) of the hsync pulse in which the captured data is ?0x00? and the auto - tune stops. defau lt: 0000 0000b 0x02c vertical mask window begin r/w bits name description 7 - 0 gi_vmask_beg [7:0] vertical mask window begin. when gi_mkwin_en =1, this register sets the number of lines after the referenced edge (cr:0x020[7]) of the vsync pulse in which t he captured data is ?0x00? and auto - tune starts outside this window. default: 0000 0000b 0x02d vertical mask window end r/w bits name description 7 - 0 gi_vmask_end [7:0] vertical mask window end. when gi_mkwin_en =1, this register sets the number of lin es before the referenced edge (cr:0x020[7]) of the vsync pulse in which the captured data is ?0x00? and the auto - tune stops. default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 58 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. active cap_hbeg cap_hwid cap_vbeg cap_vlen vs hs capture window control figure 8.4 - 1 capture window contro l 0x02e capture vertical begin for odd field ? lo r/w bits name description 7 - 0 gi_cap_vbego [7:0] vertical capture begin for odd field. gi_cap_vbego indicates how many lines to wait after referenced edge (cr:0x020[7]) of vsync before starting image captu re. gi_cap_vbego =3, means waiting 3 lines to begin capture. this register is double - buffered. default: 0000 0000b 0x02f capture vertical begin for odd field ? hi r/w bits name description 7 - 3 reserved 2 - 0 gi_cap_vbego [10:8] msb of gi_cap_vbego. this register is double - buffered. default: 0000 0000b 0x030 capture vertical begin for even field ? lo r/w bits name description 7 - 0 gi_cap_vbege [7:0] vertical capture begin for even field. gi_cap_vbege indicates how many lines to wait after referenced edge (cr:0x020[7]) of vsync before starting image capture. gi_cap_vbege =3, means waiting 3 lines to begin capture. this register is double - buffered. default: 0000 0000b 0x031 capture vertical begin for even field ? hi r/w bits name description 7 - 3 reserved 2 - 0 gi_cap_vbege [10:8] msb of gi_cap_vbege. this register is double - buffered. default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 59 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x032 capture vertical length ? lo r/w bits name description 7 - 0 gi_cap_vlen [7:0] vertical capture length. gi_cap_vlen indicates how many lines to capt ure. gi_cap_vlen = 3, means capturing 3 lines. this register is double - buffered. default: 0000 0000b 0x033 capture vertical length ? hi r/w bits name description 7 - 3 reserved 2 - 0 gi_cap_vlen [10:8] msb of gi_cap_vlen. this register is double - buffered . default: 0000 0000b 0x034 capture horizontal begin ? lo r/w bits name description 7 - 0 gi_cap_hbeg [7:0] horizontal capture begin. gh_cap_hbeg indicates how many pixels to wait after referenced edge (cr:0x020[3]) of hsync before starting image capture. gh_cap_hbeg =3, means waiting 3 pixels to begin capture. this register is double - buffered. default: 0000 0000b 0x035 capture horizontal begin ? hi r/w bits name description 7 - 4 reserved 3 - 0 gi_cap_hbeg [11:8] msb of gi_cap_hbeg. this register is doub le - buffered. default: 0000 0000b 0x036 capture horizontal width ? lo r/w bits name description 7 - 0 gi_cap_hwid [7:0] horizontal capture width. gi_cap_hwid indicates how many pixels to capture. gi_cap_hwid = 3, means capturing 3 pixels. this register is double - buffered. default: 0000 0000b 0x037 capture horizontal width ? hi r/w bits name description 7 - 4 reserved 3 - 0 gi_cap_hwid [11:8] msb of gi_cap_hwid. this register is double - buffered. default: 0000 0000b 0x038 capture clk invert r/w bits name d escription 7 - 5 reserved 4 capture clk invert 3 - 0 reserved default: 0000 00 00b 0x039 ~ 0x3b : reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 60 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x03c dvi input horizontal active width - lo r bits name description 7 - 0 dvi_cap_hwid [7:0] the active window horizontal width. the value is valid only for dvi interface is enabled and the sync input source is from dvi de signal default: xxxx xxxx b 0x03d dvi input horizontal active width - hi r bits name description 3 - 0 dvi_cap_hwid [11:8] msb of dvi_cap_hwid default: xxxx xxxx b 0x03e dvi input ver tical active length - lo r bits name description 7 - 0 dvi_cap_vlen [7:0] the active window vertical length. the value is valid only for dvi interface is enabled and the sync input source is from dvi de signal default: xxxx xxxx b 0x03f dvi input vertical ac tive length - hi r bits name description 2 - 0 dvi_cap_vlen [10:8] msb of dvi_cap_vlen default: xxxx xxxx b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 61 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8.5. video port control general control 0x040 video port control 1 r/w bits name description 7 - 5 reserved 4 uv_swap swap the order of received uv data . 0 = normal 1 = swap 3 - 2 reserved 1 vi_inte_en interlaced input enable 0 = non - interlaced 1 = interlaced 0 vi_cap_en input capture enable 0 = disabled 1 = enabled default: 0000 0000b 0x041 video port control 2 r/w bits name description 7 - 6 reserved 5 vi_cap_656_auto for bt656 mode, when vi_cap_656_auto = ?1?. hardware referee to the setting of capture registers to capture the active data 0 = disable 1 = enable 4 vi_mkwin_en mask window enable. when vi_mkwin_en =1, vi_hmask_beg, vi_hm ask_end, vi_vmask_beg and vi_vmask_end are used to set the window around the hsync and vsync during which the captured data is 0x00 and auto tune is disabled. this filters out noise occurring on the rgb channels around the hsync and vsync pulse. 0 = disa ble 1 = enable 3 vi_wrap_sel wrap around method select 0 = wrap around 1 = wrap black 2 vi_sync_edge select the h/v sync reference edge. 0 = leading edge 1 = trailing edge 1 vcap_656_en for bt656 mode, active data is enclosed by sav/eav code. hard ware can automatically capture the active data and bypass the setting of capture registers except the horizontal capture width. 0 = according to vertical capture registers 1 = according to sav/eav code 0 hcap_656_en for bt656 mode, active data is enclos ed by sav/eav code. hardware can automatically capture the active data and bypass the setting of capture registers except the horizontal capture width. 0 = according to horizontal capture registers 1 = according to sav/eav code default: 0000 0000b 0x042 polarity control r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 62 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name description 7 - 6 reserved 5 vi_656clk_inv invert the polarity of clk for internal bt656 data processing unit 0 = normal 1 = invert 4 vi_ifld_inv invert the internal field reference signal for data merging priority 0 = normal 1 = invert 3 - 0 reserved default: 0000 0000b 0x043 vsync delay r/w bits name description 7 - 4 reserved 3 - 0 vi_vsdly [3:0] delay the video port vsync pulse by input pixel clock to avoid the confusion of 1 st hsync recognized following vsync t railing edge. 0~15 pixels delay default: 0000 0001b 0x044 ~ 0x46 : reserved mask window define 0x047 horizontal mask window begin r/w bits name description 7 - 0 vi_hmask_beg [7:0] horizontal mask window begin. when vi_mkwin_en =1, this register sets the number of clocks after the referenced edge (cr:0x041[2]) of the hsync pulse in which the captured data is ?0x00? and the auto - tune starts outside this window. default: 0000 0000b 0x048 horizontal mask window end r/w bits name description 7 - 0 vi_hmask_e nd [7:0] horizontal mask window end. when vi_mkwin_en =1, this register sets the number of clocks before the referenced edge (0x041[2]) of the hsync pulse in which the captured data is ?0x00? and the auto - tune stops. default: 0000 0000b 0x049 vertical ma sk window begin r/w bits name description 7 - 0 vi_vmask_beg [7:0] vertical mask window begin. when vi_mkwin_en =1, this register sets the number of lines after the referenced edge (cr:0x041[2]) of the vsync pulse in which the captured data is ?0x00? and a uto - tune starts outside this window. default: 0000 0000b 0x04a vertical mask window end r/w bits name description 7 - 0 vi_vmask_end [7:0] vertical mask window end. when vi_mkwin_en =1, this register sets the number of lines before the referenced edge (c r:0x041[2]) of the vsync pulse in which the captured data is ?0x00? and the auto - tune free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 63 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. stops. default: 0000 0000b 8.6. color space conversion control color transfer equation r = y 601 + coefa*(cr - 128)/512 g = y 601 ? coefb*(cr - 128)/512 ? coefc*(cb - 128)/512 b = y 601 + coefd*(cb - 128)/512 sdtv r = y 601 + 1.371(cr - 128) g = y 601 ? 0.698(cr - 128) ? 0.336(cb - 128) b = y 601 + 1.732(cb - 128) hdtv r = y 709 + 1.540(cr - 128) g = y 709 ? 0.459(cr - 128) ? 0.183(cb - 128) b = y 709 + 1.816(cb - 128) color transfer coefficient 0x04b c olor transfer coefficient d ? lo r/w bits name description 7 - 0 coefd [7:0] video yuv/ypbpr to rgb color transfer coefficient. 0~1023 default: 1011 1110b 0x04c color transfer coefficient d ? hi r/w bits name description 7 - 2 reserved 1 - 0 coefd [9:8] ms b of coefd default: 0000 0010b 0x04d color transfer coefficient c ? lo r/w bits name description 7 - 0 coefc [7:0] video yuv/y p bpr to rgb color transfer coefficient. 0~1023 default: 0110 0101b 0x04e color transfer coefficient c ? hi r/w bits name descri ption 1 - 0 coefc [9:8] msb of coefc default: 0000 0001b 0x04f color transfer coefficient b ? lo r/w bits name description 7 - 0 coefb [7:0] video yuv/y p bpr to rgb color transfer coefficient. 0~1023 default: 1010 1100b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 64 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x050 color transfer coefficient b ? hi r/w bits name description 1 - 0 coefb [9:8] msb of coefb default: 0000 0000b 0x051 color transfer coefficient a ? lo r/w bits name description 7 - 0 coefa [7:0] video yuv/y p bpr to rgb color transfer coefficient. 0~1023 default: 0111 0111b 0x052 colo r transfer coefficient a ? hi r/w bits name description 1 - 0 coefa [9:8] msb of coefa default: 0000 0011b 8.7. video port capture control capture window control 0x053 vertical capture begin for odd field ? lo r/w bits name description 7 - 0 vi_cap_vbego [7:0] odd field vertical capture begin. vi_cap_vbego indicates how many lines to wait after referenced edge (cr:0x041[2]) of vsync before starting image capture. vi_cap_vbego =3, means waiting 3 lines to begin capture. this register is double - buffered. default : 0000 0000b 0x054 vertical capture begin for odd field ? hi r/w bits name description 2 - 0 vi_cap_vbego [10:8] msb of vi_cap_beg. this register is double - buffered. default: 0000 0000b 0x055 vertical capture begin for even field ? lo r/w bits name descri ption 7 - 0 vi_cap_vbege [7:0] even field vertical capture begin. vi_cap_vbege indicates how many lines to wait after referenced edge (cr:0x041[2]) of vsync before starting image capture. vi_cap_vbege =3, means waiting 3 lines to begin capture. this regist er is double - buffered. default: 0000 0000b 0x056 vertical capture begin for even field ? hi r/w bits name description 2 - 0 vi_cap_vbege [10:8] msb of vi_cap_vbege. this register is double - buffered. default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 65 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x057 vertical capture length ? lo r /w bits name description 7 - 0 vi_cap_vlen [7:0] vertical capture length. vi_cap_vlen indicates how many lines to capture. vi_cap_vlen =3, means capturing 3 lines. this register is double - buffered. default: 0000 0000b 0x058 vertical capture length ? hi r/w bits name description 2 - 0 vi_cap_vlen [10:8] msb of vi_cap_vlen. this register is double - buffered. default: 0000 0000b 0x059 horizontal capture begin ? lo r/w bits name description 7 - 0 vi_cap_hbeg [7:0] horizontal capture begin. vi_cap_hbeg indica tes how many pixels to wait after referenced edge (cr:0x041[2]) of hsync before starting image capture. vi_cap_hbeg =3, means waiting 3 pixels to begin capture. this register is double - buffered. default: 0000 0000b 0x05a horizontal capture begin ? hi r/w bits name description 3 - 0 vi_cap_hbeg [11:8] msb of vi_cap_hbeg. this register is double - buffered. default: 0000 0000b 0x05b horizontal capture width ? lo r/w bits name description 7 - 0 vi_cap_hwid [7:0] horizontal capture width. vi_cap_hwid indicates how many pixels to capture. vi_cap_hwid = 3, means capturing 3 pixels. this register is double - buffered. default: 0000 0000b 0x05c horizontal capture width ? hi r/w bits name description 3 - 0 vi_cap_hwid [11:8] msb of vi_cap_hwid this register is double - buffered. default: 0000 0000b 0x05d ~ 0x5f : reserved 8.8. back end image processing ? back - end offset control ? back - end gain control ? back - end sharpness and smooth control 0x060 back - end horizontal sharpness r/w bits name description 7 reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 66 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6 bk_h_asr p graphic horizontal adaptive sharpness adjusting. 0 = disable 1 = enable 5 reserved 4 bk_h_srpsmo graphic horizontal back - end smooth and sharpness select. 0 = sharpness 1 = smooth 3 - 0 bk_h_srp [3:0] graphic horizontal back - end sharpness/smooth a djusting. 16 steps default: 0000 0000b 0x061 : reserved 0x062 gamma fixed bit r/w bits name description 7 - 6 reserved 5 - 4 b[1:0] fixed ?00? , ?01? , ?10? , ?11? 3 - 2 g[1:0] fixed ?00? , ?01? , ?10? , ?11? 1 - 0 r[1:0] fixed ?00? , ?01? , ?10? , ?11? default: 0000 0000b 0x063 gamma fixed bit enable r/w bits name description 7 - 3 reserved 2 b enable , gamma disable or gamma 10 bit out [1:0] = ?00? 1 g enable , 0 r enable default: 0 000 0000b 0x064 interpolation control r/w bits name descript ion 7 - 5 text_en [2:0] select the text mode type 000 = normal mode 001 = level 1 text mode 010 = level 2 text mode 011 = level 3 text mode 1xx = reserved 4 - 3 v_inte_type [1:0] select the vertical interpolation type 00 = dsp (2 - pixel) 01 = bi - linea r (2 - pixel) 10 = duplicate (2 - pixel) 11 = reserved 2 - 0 h_inte_type [2:0] select the horizontal interpolation type 000 = advanced dsp (4 - pixel) 001 = bi - linear (2 - pixel) 010 = duplicate (2 - pixel) 011 = dsp (2 - pixel) 100 = dsp (4 - pixel) 101, 110, 1 11 = reserved default: 0000 0000b 0x065 gamma control r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 67 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name description 7 gamma_en gamma table enable, when gamma_en = 1, the gamma table can?t read or write by host interface. when gamma_en = 0 the display is bypass the gamma table. 0 = disab le 1 = enable 6 - 0 reserved default: 0000 0000b 0x066 back - end vertical sharpness r/w bits name description 7 - 3 reserved 2 - 0 int_v_sharp [2:0] vertical interpolation sharpness adjusting 8 steps default: 0000 0000b 0x067 : reserved 8.9. noise reduction filter control 0x068 noise reduction filter control r/w bits name description 7 reserved 6 nr2_en second noise reduction enable , nr2_thr[3:0] ( cr: 0x06b ) adjust the threshold ( nr_type = ?001? , ?010? , ?011? ) 0 = disable 1 = enable 5 nr_round noise reduction round calculation enable ( nr_type = ?001? , ?010? , ?011? ) 0 = disable 1 = enable 4 nr_edge_det noise reduction edge detection enable , nr_edge_thr[3:0] ( 0x069 ) adjust the threshold ( nr_type = ?001? , ?010? , ?011? ) 0 = disable 1 = enable 3 reserved 2 - 0 nr_type select the noise reduction filter type 000 = normal mode (nr disable) 001 = mode 1 010 = mode 2 011 = mode 3 , nr_thr[3:0] ( 0x069 ) adjust the threshold 1xx = reserved default: 0000 0000b 0x069 noise reduction th reshold r/w bits name description 7 - 4 nr_edge_thr [3:0] edge threshold of the noise reduction filter adjusting. 0x068[4] must be set ?1? 3 - 0 nr_thr [3:0] threshold of the noise reduction filter adjusting. 0x068[2:0] must be set ?001? or ?010? or ?011? default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 68 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x06a adc high pass filter r/w bits name description 7 - 6 reserved 5 nr_dither _rst nr random dither reset mode ( 0x06b.4 nr_dither must set random mode ) 0 = disable 1 = enable 4 adc_hpass_en adc high pass filter 0 = disable 1 = enable 3 reserved 2 - 0 adc_hpass [ 2 :0] adc high pass filter level default: 0000 000 0 b 0x06b seconded noise reduction threshold r/w bits name description 7 - 6 reserved 5 ghost_cancel ghost cancellation 0 = disable 1 = enable 4 nr_dither nr dithe r mode : 0: order mode 1: random mode 3 - 0 nr2_thr [3:0] threshold of the seconded noise reduction filter adjusting. cr: 0x068[6] must be set ?1? default: 0000 0000b 0x06 c : reserved 0x 06 d nr reset dither frame invert r/w bits name description 7 - 6 r eserved 5 - 4 nr_rst_inv nr dither reset mode frame invert count 00: 1 frame 01: 2 frame 10: 3 frame 11: 4 frame 3 - 1 reserved 0 nr_rst_inv nr dither reset mode frame invert enable default: 0000 0000b 0x06 e ~ 0x6f : reserved 8.10. general purpose input outpu t (gpio) 0x070 gpio port control r/w bits name description 5 pwma_en pwma output enable (open - drain) 0 = disable 1 = pwma enable free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 69 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 4 pwmb_en pwmb output enable (open - drain) 0 = disable 1 = pwmb enable 3 - 0 reserved default: 0000 0000b 0x071 ~ 0x073 : reserved 8.11. pwm output ? frequency programmable ? duty cycle programmable pwm_hcnt pwm_lcnt pwm_clk when clock source select from reference clock ) pwm_div (pwm_div f f refclk pwm_clk 2 1 ? ? when clock source select from display hsync ) pwm_div (pwm_div f f hs disp pwm_clk 2 1 _ ? ? pwm pwm_clk pwm pwm_clk pwm_clk pwm f f duty lcnt pwm f f duty hcnt pwm pwm_lcnt pwm_hcnt hcnt pwm duty pwm_lcnt) (pwm_hcnt f f ? ? ? ? ? ? ? ? ? ) 1 ( _ _ ) ( _ pwm _hcnt pwm_lcnt pwm output 0 0 tri - state 0 1~255 dc ?0? 1~255 0 dc ?1? 1~255 1~255 pwm pulse 0x074 pwmb low period counter r/w bits name description 7 - 0 pwmb_lcnt [7:0] pwmb pulse low period counter value. c ount with 12m or display hs double - buffere d. default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 70 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x075 pwmb high period counter r/w bits name description 7 - 0 pwmb_hcnt [7:0] pwmb pulse high period counter value. c ount with 12m or display hs double - buffered. default: 0000 0000b 0x076 pwma low period counter r/w bits name des cription 7 - 0 pwma_lcnt [7:0] pwma pulse low period counter value. c ount with 12m or display hs double - buffered. default: 0000 0000b 0x077 pwma high period counter r/w bits name description 7 - 0 pwma_hcnt [7:0] pwma pulse high period counter value. c ount with 12m or display hs double - buffered. default: 0000 0000b 0x078 ~ 0x7d : reserved 0x07e pwm control 1 r/w bits name description 7 pwma_vs_lock pwma counter lock to display vertical sync 0 = roll pwm counter over continuously 1 = load pwm on display vs (disp_vs) leading edge 6 - 5 pwma_div1 [1:0] first divider ? pwma clock divide of the selected clock by 00 = 1; 01 = 2; 10 = 4; 11 = 8 4 pwma_clk pwma clock source select 0 = reference clock 1 = display hs (disp_hs) 3 pwmb_vs_lock pwmb counter lock t o display vertical sync 0 = roll pwm counter over continuously 1 = load pwm on display vs (disp_vs) leading edge 2 - 1 pwmb_div1 [1:0] first divider ? pwmb clock divide of the selected clock by 00 = 1; 01 = 2; 10 = 4; 11 = 8 0 pwmb_clk pwmb clock source s elect 0 = reference clock 1 = display hs (disp_hs) default: 0000 0000b 0x07f pwm control 2 r/w bits name description 7 pwma_vsreset pwma reset counter on dsip_vs leading edge 0 = roll pwma counter over continuously 1 = reset pwma on disp_vs leading edge 6 pwmb_vsreset pwmb reset counter on dsip_vs leading edge 0 = roll pwmb counter over continuously 1 = reset pwmb on disp_vs leading edge 5 - 4 reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 71 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 3 - 2 pwma_ div2 second divider ? pwma clock divide of the selected clock by 00 = 1; 01 = 16 10 = 256 ; 11 = 4096 1 - 0 pwmb_div2 [1:0] second divider ? pwmb clock divide of the selected clock by 00 = 1; 01 = 16 10 = 256 ; 11 = 4096 default: 0000 0000b 8.12. on screen display registers osd control 0x080 osd and window enable c ontrol r/w bits name description 7 rot_en rotation control. 0: normal 1: rotated 6 flip_en flip control 0: no flip 1: flip on 5 mir_en mirror control 0: no mirror 1: mirror on 4 win4_en enable window 4 0: disable 1: enable 3 win3_en enable w indow 3 0: disable 1: enable 2 win2_en enable window 2 0: disable 1: enable 1 win1_en enable window 1 0: disable 1: enable 0 osd_en enable osd 0: disable 1: enable default: 0000 0000b 0x081 osd frame horizontal start ? low byte r/w bits name description 7 - 0 osd_hs [7:0] osd frame horizontal start low byte [7:0]. specifies the horizontal starting position of the osd in pixel units. this register is double - buffered . default: 0000 0000b 0x082 osd frame horizontal start ? high byte r/w bits name description 7 - 4 reserved 3 - 0 osd_hs [11:8] osd frame horizontal start high byte [11:8]. specifies the horizontal starting position of the osd in pixel units. this register is double - buffered . free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 72 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. default: 0000 0000b 0x083 osd frame horizo ntal width r/w bits name description 7 reserved 5 - 0 osd_hw [5:0] specifies the width of the osd in font units. range: 0~ 63 (osd display width = 1~64) default: 0000 0000b 0x084 osd frame vertical start low byte r/w bits name description 7 - 0 osd_vs [7:0] osd frame vertical start low byte [7:0]. specifies the vertical starting position of the osd in line units. this register is double - buffered . default: 0000 0000b 0x085 osd frame vertical start high byte r/w bits name description 7 - 3 reserved 2 - 0 osd_vs [10:8] osd frame vertical start high byte [10:8]. specifies the vertical starting position of the osd in line units. this register is double - buffered . default: 0000 0101b 0x086 osd frame vertical height r/w bits name description 7 - 5 reserved 4 - 0 osd_vh [4:0] specifies the height of the osd in font units. range: 0~31 (osd display height = 1~32) default: 0000 0000b 0x087 osd shift row offset r/w bits name description 4 - 0 osd_shift_row specifies the row of the osd shift offset. t op row will shift to bottom and like rolling function . range: 0~31 default: 0000 0000b 0x088 osd one bit font address ? low byte r/w bits name description 7 - 0 font1b_addr [7:0] osd one bit per pixel programmable font start addres s high byte [7:0]. specifies the start address for the on - chip programmable font. default for this 12 bit register = 1000 (dec) default: 1110 1000b 0x089 osd one bit font address ? high byte r/w bits name description 3 - 0 font1b_addr [11:8] osd one bit per pixel programmable font start address high byte [11:8]. specifies the start address for the on - chip programmable font default for this 12 bit register = 1000 (dec) default: 0000 0011b 0x08a osd two bit font address ? low byte r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 73 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name descr iption 7 - 0 font2b_addr [7:0] osd two bit per pixel programmable font start address high byte [7:0]. specifies the start address for the on - chip programmable font. default for this 12 bit register = 2656 (dec) default: 0110 0000b 0x08b osd two bit f ont address ? high byte r/w bits name description 3 - 0 font2b_addr [11:8] osd two bit per pixel programmable font start address high byte [11:8]. specifies the start address for the on - chip programmable font default for this 12 bit register = 2656 ( dec) default: 0000 1010b 0x08c osd three/four bit font address ? low byte r/w bits name description 7 - 0 font4b_addr [7:0] osd three/four bit per pixel programmable font start address high byte [7:0]. specifies the start address for the on - chip pro grammable font. if 0x09f[7] = ?1? , this register for three bit font address low byte default for this 12 bit register = 3808 (dec) default: 1110 0000b 0x08d osd three/four bit font address ? high byte r/w bits name description 3 - 0 font4b_addr [11 :8] osd three/four bit per pixel programmable font start address high byte [11:8]. specifies the start address for the on - chip programmable font if 0x09f[7] = ?1? , this register for three bit font address high byte default for this 12 bit register = 3808 (dec) default: 0000 1110b osd fade in/out control 0x08e osd fade - in / fade - out step r/w bits name description 7 - 4 fad_v_step [3:0] osd vertical side fade - in / fade - out step (4 pixel/step) 0~15 step 3 - 0 fad_h_step [3:0] osd horizontal side fade - in / fade - out step (4 pixel/step) 0~15 step default: 0000 0000b 0x08f osd fade - in / fade - out frequency r/w bits name description 7 fad_en fade - in / fade - out function enable. 0: fade - in / fade - out disable 1: fade - in / fade - out enable 6 - 4 fad_vfreq [ 2:0] osd fade - in / fade - out vertical frequency for every step (4 frame/step) 3 - 0 fad_hfreq [3:0] osd fade - in / fade - out horizontal frequency for every step (4 frame/step) default: 0000 0000b osd zoom control 0x090 osd zoom control for separate row contro l disable r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 74 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name description 7 - 4 reserved 3 vrow_zmen vertical row zoom enable; vertical zoom for all characters in one row defined in reg 0x09a ~ 0x09d. 0: disable 1: enable. 2 hrow_zmen horizontal row zoom enable; horizontal zoom for all characters in one row defined in reg 0x096 ~ 0x099. 0: disable 1: enable. 1 vglob_zmen vertical global zoom enable; vertical zoom for all characters in osd frame. 0: disable 1: enable. 0 hglob_zmen horizontal global zoom enable; horizontal zoom for all characters in osd frame. 0: disable 1: enable. default: 0000 0000b 0x090 osd zoom control for separate row control enable r/w bits name description 7 - 6 row_v_zmrng1 [1:0] row zoom range this is a user definable zoom pattern. pixels with ?1? pattern that define at 0x092 ~ 0x094 are duplicated according to the zoom range. 5 - 4 row_v_zmrng0 [1:0] row zoom range this is a user definable zoom pattern. pixels with ?0? pattern that define at 0x092 ~ 0x094 are duplicated according to the zoom ran ge. 3 - 1 row_space separate row vertical space , the row select at 0x09f[4:0] 0 hglob_zmen row vertical zoom 0: disable 1: enable. default: 0000 0000b 0x091 osd font horizontal global zoom pattern ? low byte r/w bits name description 7 - 0 hzm_pa tn [7:0] least significant 8 bits (7:0) of the horizontal zoom pattern. this is a user definable zoom pattern. pixels with ?1? pattern are duplicated according to the zoom range. default: 0000 0000b 0x092 osd font horizontal/vertical global zoom pattern ? high byte r/w bits name description 7 - 6 reserved 5 - 4 vzm_patn [17:16] most significant 2 bits (17:16) of the vertical zoom pattern. this is a user definable zoom pattern. pixels with ?1? pattern are duplicated according to the zoom range. 3 - 0 hzm_patn [11:8] most significant 4 bits (11:8) of the horizontal zoom pattern. this is a user definable zoom pattern. pixels with ?1? pattern are duplicated according to the zoom range. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 75 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. default: 0000 0000b 0x093 osd font vertical global zoom pattern ? low byte r/w bits name description 7 - 0 vzm_patn [7:0] least significant 8 bits (7:0) of the vertical zoom pattern. this is a user definable zoom pattern. pixels with ?1? pattern are duplicated according to the zoom range. default: 0000 0000b 0x0 94 osd font vertical global zoom pattern ? mid byte r/w bits name description 7 - 0 vzm_patn [15:8] bits (15:8) of the vertical zoom pattern. this is a user definable zoom pattern. pixels with ?1? pattern are duplicated according to the zoom range. default: 0000 0000b 0x095 osd font global zoom range r/w bits name description 7 - 6 vglob_zmrng1 [1:0] vertical global zoom pattern (reg 0x092 ~ 0x094) ?1? zoom range 00: no zoom 01: vertical zoom pattern ?1? bits are duplicated once 10: vertical zoom pattern ?1? bits are duplicated twice 11: vertical zoom pattern ?1? bits are duplicated three times 5 - 4 hglob_zmrng1 [1:0] horizontal global zoom pattern (reg 0x091 ~ 0x092) ?1? zoom range 00: no zoom 01: horizontal zoom pattern ?1? bits are dupli cated once 10: horizontal zoom pattern ?1? bits are duplicated twice 11: horizontal zoom pattern ?1? bits are duplicated three times 3 - 2 vglob_zmrng0 [1:0] vertical global zoom pattern (reg 0x092 ~ 0x094) ?0? zoom range 00: no zoom 01: vertical zoom patte rn ?0? bits are duplicated once 10: vertical zoom pattern ?0? bits are duplicated twice. 11: vertical zoom pattern ?0? bits are duplicated three times. 1 - 0 hglob_zmrng0 [1:0] horizontal global zoom pattern (reg 0x091 ~ 0x092) ?0? zoom range 00: no zoom 0 1: horizontal zoom pattern ?0? bits are duplicated once 10: horizontal zoom pattern ?0? bits are duplicated twice 11: horizontal zoom pattern ?0? bits are duplicated three times default: 0000 0000b 0x096 horizontal row zoom control row 7 ? 0 r/w bits na me description 7 - 0 hrow_zmpn [7:0] horizontal row zoom pattern 7 - 0 zooms each row horizontally defined as zoom range according to each bit. each bit controls a row correspondingly. reg 0x090 [2] must be set to ?1?. default: 0000 0000b 0x097 horizo ntal row zoom control row 15 ? 8 r/w bits name description 7 - 0 hrow_zmpn [15:8] horizontal row zoom pattern 15 - 8 zooms each row horizontally defined as zoom range according to each bit. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 76 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. each bit controls a row correspondingly. reg 0x090 [2] must be set to ?1?. default: 0000 0000b 0x098 horizontal row zoom control row 23 ? 16 r/w bits name description 7 - 0 hrow_zmpn [23:16] horizontal row zoom pattern 23 - 16 zooms each row horizontally defined as zoom range according to each bit. each bit cont rols a row correspondingly. reg 0x090 [2] must be set to ?1?. default: 0000 0000b 0x099 horizontal row zoom control row 31 ? 24 r/w bits name description 7 - 0 hrow_zmpn [31:24] horizontal row zoom pattern 31 - 24 zooms each row horizontally defined a s zoom range according to each bit. each bit controls a row correspondingly. reg 0x090 [2] must be set to ?1?. default: 0000 0000b 0x09a vertical row zoom control row 7 ? 0 r/w bits name description 7 - 0 vrow_zmpn [7:0] vertical row zoom pattern 7 - 0 zooms each row vertically defined as zoom range according to each bit. each bit controls a row correspondingly. reg 0x090 [3] must be set to ?1?. default: 0000 0000b 0x09b vertical row zoom control row 15 ? 8 r/w bits name description 7 - 0 vrow_z mpn [15:8] vertical row zoom pattern 15 - 8 zooms each row vertically defined as zoom range according to each bit. each bit controls a row correspondingly. reg 0x090 [3] must be set to ?1?. default: 0000 0000b 0x09c vertical row zoom control row 23 ? 16 r/ w bits name description 7 - 0 vrow_zmpn [23:16] vertical row zoom pattern 23 - 16 zooms each row vertically defined as zoom range according to each bit. each bit controls a row correspondingly. reg 0x090 [3] must be set to ?1?. default: 0000 0000b 0x 09d vertical row zoom control row 31 ? 24 r/w bits name description 7 - 0 vrow_zmpn [31:24] vertical row zoom pattern 31 - 24 zooms each row vertically defined as zoom range according to each bit. each bit controls a row correspondingly. reg 0x090 [3] must be set to ?1?. default: 0000 0000b 0x09e osd font row zoom range r/w bits name description 7 - 4 reserved 3 - 2 vrow_zmrng [1:0] vertical row zoom range; the rows assigned by vertical row zoom control registers will be zoomed up. 00: vertical zoom 1x for all fonts in the row free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 77 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 01: vertical zoom 2x for all fonts in the row 10: vertical zoom 3x for all fonts in the row 11: vertical zoom 4x for all fonts in the row 1 - 0 hrow_zmrng [1:0] horizontal row zoom range; the rows assigned by horizontal row zoom control registers will be zoomed up. 00: horizontal zoom 1x for all fonts in the row 01: horizontal zoom 2x for all fonts in the row 10: horizontal zoom 3x for all fonts in the row 11: horizontal zoom 4x for all fonts in the row default: 0000 00 00b 0x09f separate row control r/w bits name description 7 three_bit_font three bit font 0: disable 1: enable 6 separate_row_en 32 separat row control 0: disable 1: enable 5 row_access row access 0: disable 1: enable 4 - 0 row_select 32 row sele ct default: 0000 0000b osd translucent and blinking control 0x0a0 osd blink control r/w bits name description 7 reserved 6 osd_blink blink 0=blink control from font attribute bit 0. 1=osd frame blink enable, don?t care the attribute bit 0. 5 bs _blink mask border/shadow at blink 0= character border/shadow will blink with the foreground of the character. 1=character border/shadow will not blink with the foreground of the character. 4 - 2 blink_freq [2:0] blink frequency 000: character foreground?s blinking period is 4 frames. 001: character foreground?s blinking period is 8 frames. 010: character foreground?s blinking period is 16 frames. 011: character foreground?s blinking period is 32 frames. 100: character foreground?s blinking period is 64 fram es. 1 - 0 blink_rate [1:0] blink rate 00: character foreground is turned 25% on / 75% off. 01: character foreground is turned 50% on / 50% off. 10: character foreground is turned 75% on / 25% off. 11: reserved. default: 0000 0001b 0x0a1 osd character tran slucent level r/w bits name description 7 - 6 reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 78 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 5 - 3 tp_level_two [2:0] when the attribute bg_index is set to ?0001?, these 3 - bits set the translucent level of the character background color. translucent level refers to the percentage of colo r composition that is osd. ?111? = 0% ?110? = 12.25% ?101? = 25% ?100? = 37.5% ?011? = 50% ?010? = 62.5% ?001? = 75% ?000? = 87.5% 2 - 0 tp_level_one [2:0] when the attribute bg_index is set to ?0000? ~ ?1111? except ?0001?, these 3 - bit s set the translucent level of the character background color. translucent level refers to the percentage of color composition that is osd. ?111? = 0% ?110? = 12.25% ?101? = 25% ?100? = 37.5% ?011? = 50% ?010? = 62.5% ?001? = 75% ?000? = 87.5% default: 0000 0000b osd spacing control 0x0a2 osd space r/w bits name description 7 v_fs_sel vertical font size selection 0: 18 font size for vertical 1: 16 font size for vertical 6 h_fs_sel horizontal font size selection 0: 12 font siz e selected for horizontal 1: 10 font size selected for horizontal 5 - 3 vspace [2:0] osd vertical space. these 3 bits define the vertical scan pixel of background color added to above and below of each character. range: 0~7 2 - 0 hspace [2:0] osd horizontal space. these 3 bits define the horizontal scan pixel of background color added to left and right of each character. range: 0~7 default: 0000 0000b 0x0 a3 osd window/font gradient control ? 1 r/w bits name description 7 grd_b_pol windrow/font gradie nt blue polarity 0: increase 1: decrease 6 grd_g_pol windrow/font gradient green polarity 0: increase 1: decrease 5 grd_r_pol windrow/font gradient red polarity 0: increase 1: decrease 4 grd_direct windrow gradient direction 0: horizontal direction 1: v ertical direction 3 grd_b_en windrow gradient blue 0: disable 1: enable free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 79 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 2 grd_g_en windrow gradient green 0: disable 1: enable 1 grd_r_en windrow gradient red 0: disable 1: enable 0 win_grd_en windrow gradient , the palette index define at 0x0ab 0: bac kground gradient enable 1: foreground gradient enable default: 0000 0000b 0x0 a4 osd window gradient control - 2 r/w bits name description 7 - 4 win_grd_step window gradient step , define decrease or increase level each step 3 - 0 win_grd_pix window gra dient pixel , define how many pixel decrease or increase level each step default: 0000 0000b osd window control 0x0a5 osd window select r/w bits name description 7 win8_en enable window 8 0: disable 1: enable 6 win7_en enable window 7 0: disable 1: enable 5 win6_en enable window 6 0: disable 1: enable 4 win5_en enable window 5 0: disable 1: enable 3 reserved 2 - 0 win_sel [2:0] this register is used to select which window is to be accessed or modified. it is programmed prior to accessing the registers reg 0x0a6h ~ 0x0a f h ?000? = window1 ?001? = window2 ?010? = window3 ?011? = window4 ?100? = window5 ?101? = window6 ?110? = window7 ?111? = window8 default: 0000 0000b 0x0a6 osd window horizontal start r/w bits name description 7 - 6 reserved 5 - 0 win_hs [5:0] horizontal starting position relative to the osd for the selected window. the unit is in font. range: 0~63 default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 80 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x0a7 osd window horizontal end r/w bits name description 7 - 6 reserved 5 - 0 win_ he [5:0] horizontal ending position relative to the osd for the selected window. the unit is in font. the osd window horizontal width = (win_he+1) ? win_hs range: 0~63 default: 0000 0000b 0x0a8 osd window vertical start r/w bits name description 4 - 0 win_vs [4:0] vertical starting position relative to the osd for the selected window. the unit is in font. range: 0~31 default: 0000 0000b 0x0a9 osd window vertical end r/w bits name description 7 - 5 reserved 4 - 0 win_ve [4:0] vertical ending position relative to the osd for the selected window. the unit is in font. the osd window 1 vertical height = (win1_ve+1) ? win1_vs range: 0~31 default: 0000 0000b 0x0aa osd window attribute r/w bits name description 7 win_blen window bevel enabl e bevel size is specified in 0x0ad[2:0] : win_bl_width 6 - 5 win_bl_type window bevel type 00:type1,left/bottom color define at 0x0af,right/top color define at 0x0ac or 0x0ae 01:type2,left/top color define at 0x0af,right/bottom color define at 0x0ac or 0x0a e 10:type3,top/bottom color define at 0x0af,left/right color define at 0x0ac or 0x0ae 11:reserved 4 win_mix window translucent enable for the selected window 0 ? normal 1 ? translucent ((1 - tp_level_one) * display + (tp_level_one) * osd_bg) 3 - 2 win_sdsz [1:0] shadow size for the selected window when window shadow enable 00: 2 pixels in width and 2 lines in height. 01: 4 pixels in width and 4 lines in height. 10: 6 pixels in width and 6 lines in height. 11: 8 pixels in width and 8 lines in height. 1 win_ sden window shadow enable for the selected window shadow size is specified in bits 3:2. 1= shows a shadow for window. 0= no shadow free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 81 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0 win_fade window gradient fade in/out 0: disable 1: enable default: 0000 0000b 0x0ab osd window color r/w bits name de scription 7 - 0 win_cl [7:0] color index for the selected osd window. this color will cover the character background color when window is enabled. default: 0000 0000b 0x0ac osd gradient font color r/w bits name description 7 - 0 grad_color [7:0 ] color ind ex for foreground gradient color default: 0000 0000b 0x0ab 0x0ac 0x0ae 0x0af gradient disable window color x bevel top/right side , shadow color bevel bottom/left side color background gradient window color x bevel top/right side , shadow color bevel bottom/left side color foreground gradient window color font color bevel top/right side , shadow color bevel bottom/left side color 0x0ad osd window bevel width r/w bits name description 7 - 3 win_fade_speed window gradient fade in/out speed , based on vs count 2 - 0 win_bl_width [2:0] specifies the width of the window bevel units. range: 1~8 , units : pixel default: 0000 0000b 0x0ae osd window bevel right / shadow color r/w bits name description 7 - 0 win_bl_rcl [7:0] color inde x for all eight window?s top/right side bevel and shadow default: 0000 0000b 0x0af osd window bevel left color r/w bits name description 7 - 0 win_bl_lcl [7:0] color index for all eight window?s bottom/left side bevel default: 0000 0000b osd border and shadow control 0x0b0 osd shadow control row 7 ? 0 r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 82 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name description 7 - 0 osd_scr [7:0] character row shadow enable for 7 - 0. each bit controls each row correspondingly. used only in one bit per pixel font. 1= enable shadow for a row. de fault: 0000 0000b 0x0b1 osd shadow control row 15 ? 8 r/w bits name description 7 - 0 osd_scr [15:8] character row shadow enable for 15 - 8. each bit controls each row correspondingly. used only in one bit per pixel font. 1= enable shadow for a row. default: 0000 0000b 0x0b2 osd shadow control row 23 ? 16 r/w bits name description 7 - 0 osd_scr [23:16] character row shadow enable for 23 - 16. each bit controls each row correspondingly. used only in one bit per pixel font. 1= enable shadow for a ro w. default: 0000 0000b 0x0b3 osd shadow control row 31 ? 24 r/w bits name description 7 - 0 osd_scr [31:24] character row shadow enable for 31 - 24. each bit controls each row correspondingly. used only in one bit per pixel font. 1= enable shadow for a row. default: 0000 0000b 0x0b4 osd border control row 7 ? 0 r/w bits name description 7 - 0 osd_bcr [7:0] character row border enable for 7 - 0. each bit controls each row correspondingly. used only in one bit per pixel font. 1= enable border for a row. default: 0000 0000b 0x0b5 osd border control row 15 - 8 r/w bits name description 7 - 0 osd_bcr [15:8] character row border enable for 15 - 8. each bit controls each row correspondingly. used only in one bit per pixel font. 1= enable border for a row. default: 0000 0000b 0x0b6 osd border control row 23 - 16 r/w bits name description 7 - 0 osd_bcr [23:16] character row border enable for 23 - 16. each bit controls each row correspondingly. used only in one bit per pixel font. 1= enable border for a row. default: 0000 0000b 0x0b7 osd border control row 31 - 24 r/w bits name description 7 - 0 osd_bcr character row border enable for 31 - 24. each bit controls each row free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 83 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. [31:24] correspondingly. used only in one bit per pixel font. 1= enable border fo r a row. default: 0000 0000b 0x0b8 osd border & shadow color row 1 ? 0 r/w bits name description 7 - 4 osd_bscr1 [3:0] character border/shadow color index for row 1. used only in one bit per pixel font. 3 - 0 osd_bscr0 [3:0] character border/shadow c olor index for row 0. used only in one bit per pixel font. default: 0000 0000b 0x0b9 osd border & shadow color row 3 ? 2 r/w bits name description 7 - 4 osd_bscr3 [3:0] character border/shadow color index for row 3. used only in one bit per pixel fo nt. 3 - 0 osd_bscr2 [3:0] character border/shadow color index for row 2. used only in one bit per pixel font. default: 0000 0000b 0x0ba osd border & shadow color row 5 ? 4 r/w bits name description 7 - 4 osd_bscr5 [3:0] character border/shadow color index for row 5. used only in one bit per pixel font. 3 - 0 osd_bscr4 [3:0] character border/shadow color index for row 4. used only in one bit per pixel font. default: 0000 0000b 0x0bb osd border & shadow color row 7 - 6 r/w bits name description 7 - 4 osd_bscr7 [3:0] character border/shadow color index for row 7. used only in one bit per pixel font. 3 - 0 osd_bscr6 [3:0] character border/shadow color index for row 6. used only in one bit per pixel font. default: 0000 0000b 0x0bc osd border & shadow c olor row 9 ? 8 r/w bits name description 7 - 4 osd_bscr9 [3:0] character border/shadow color index for row 9. used only in one bit per pixel font. 3 - 0 osd_bscr8 [3:0] character border/shadow color index for row 8. used only in one bit per pixel font . default: 0000 0000b 0x0bd osd border & shadow color row 11 ? 10 r/w bits name description 7 - 4 osd_bscr11 [3:0] character border/shadow color index for row 11. used only in one bit per pixel font. 3 - 0 osd_bscr10 [3:0] character border/shadow col or index for row 10. used only in one bit per pixel font. default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 84 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x0be osd border & shadow color row 13 ? 12 r/w bits name description 7 - 4 osd_bscr13 [3:0] character border/shadow color index for row 13. used only in one bit per pixel font. 3 - 0 osd_bscr12 [3:0] character border/shadow color index for row 12. used only in one bit per pixel font. default: 0000 0000b 0x0bf osd border & shadow color row 15 ? 14 r/w bits name description 7 - 4 osd_bscr15 [3:0] character border/shado w color index for row 15. used only in one bit per pixel font. 3 - 0 osd_bscr14 [3:0] character border/shadow color index for row 14. used only in one bit per pixel font. default: 0000 0000b 0x0c0 osd border & shadow color row 17 ? 16 r/w bits name descri ption 7 - 4 osd_bscr17 [3:0] character border/shadow color index for row 17. used only in one bit per pixel font. 3 - 0 osd_bscr16 [3:0] character border/shadow color index for row 16. used only in one bit per pixel font. default: 0000 0000b 0x0c1 osd border & shadow color row 19 ? 18 r/w bits name description 7 - 4 osd_bscr19 [3:0] character border/shadow color index for row 19. used only in one bit per pixel font. 3 - 0 osd_bscr18 [3:0] character border/shadow color index for row 18. used only i n one bit per pixel font. default: 0000 0000b 0x0c2 osd border & shadow color row 21 ? 20 r/w bits name description 7 - 4 osd_bscr21 [3:0] character border/shadow color index for row 21. used only in one bit per pixel font. 3 - 0 osd_bscr20 [3:0] cha racter border/shadow color index for row 20. used only in one bit per pixel font. default: 0000 0000b 0x0c3 osd border & shadow color row 23 - 22 r/w bits name description 7 - 4 osd_bscr23 [3:0] character border/shadow color index for row 23. used on ly in one bit per pixel font. 3 - 0 osd_bscr22 [3:0] character border/shadow color index for row 22. used only in one bit per pixel font. default: 0000 0000b 0x0c4 osd border & shadow color row 25 ? 24 r/w bits name description free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 85 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7 - 4 osd_bscr25 [3:0] character border/shadow color index for row 25. used only in one bit per pixel font. 3 - 0 osd_bscr24 [3:0] character border/shadow color index for row 24. used only in one bit per pixel font. default: 0000 0000b 0x0c5 osd border & shadow color row 27 ? 2 6 r/w bits name description 7 - 4 osd_bscr27 [3:0] character border/shadow color index for row 27. used only in one bit per pixel font. 3 - 0 osd_bscr26 [3:0] character border/shadow color index for row 26. used only in one bit per pixel font. defaul t: 0000 0000b 0x0c6 osd border & shadow color row 29 ? 28 r/w bits name description 7 - 4 osd_bscr29 [3:0] character border/shadow color index for row 29. used only in one bit per pixel font. 3 - 0 osd_bscr28 [3:0] character border/shadow color index for row 28. used only in one bit per pixel font. default: 0000 0000b 0x0c7 osd border & shadow color row 31 ? 30 r/w bits name description 7 - 4 osd_bscr31 [3:0] character border/shadow color index for row 31. used only in one bit per pixel font. 3 - 0 osd_bscr30 [3:0] character border/shadow color index for row 30. used only in one bit per pixel font. default: 0000 0000b osd splitting control 0x0c8 osd horizontal splitting control r/w bits name description 7 h_spl_en horizontal splitting ena ble 0: disable 1: enable 6 - 0 spl_hp [6:0] splitting horizontal begin position relative to the osd frame for the selected window. the unit is in 1 horizontal font size. range: 0~127 default: 0000 0000b 0x0c9 osd horizontal splitting width control r/w bit s name description 7 - 0 spl_hw [7:0] splitting horizontal width relative to the osd frame. the unit is in 8 pixels. range: 0~255 default: 0000 0000b 0x0ca osd vertical splitting control r/w bits name description 7 v_spl_en vertical splitting enable 0: disable free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 86 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 1: enable 6 reserved 5 - 0 spl_vp [5:0] splitting vertical begin position relative to the osd frame. the unit is in 1 vertical font size. range: 0~64 default: 0000 0000b 0x0cb osd vertical splitting height control r/w bits name descri ption 7 - 0 spl_vh [7:0] splitting vertical height relative to the osd frame. the unit is in 8 lines. range: 0~255 default: 0000 0000b osd attribute control and osd fast clear control 0x0cc osd attribute lsb r/w bits name description 7 - 0 os d_attr [7:0] osd attribute lsb. the register osd_attr [15:0] is use for fast clear and update code from host and attribute from register. this value is appended with the character font code. when update osd sram code from host and ?attribute from reg 0x0cc ~ 0x0cd is selected in reg 0x0e0 [7:4]. if fast clear is enable, the hardware will fill the entire sram with the values in reg 0x0ce (code) and reg 0x0cc ~ 0x0cd (attribute). default: 0000 0000b 0x0cd osd attribute msb r/w bits name description 7 - 0 osd_attr [15:8] osd attribute msb. the register osd_attr [15:0] is use for fast clear and update code from host and attribute from register. this value is appended with the character font code. when update osd sram code from host and attribute from reg 0x0cc ~ 0x0cd is selected in reg 0x0e0 [7:4]. if fast clear is enable, the hardware will fill the entire sram with the values in reg 0x0ce (code) and reg 0x0cc ~ 0x0cd (attribute). default: 0000 0000b 0x0ce osd sram code value for fast clear r/w bits nam e description 7 - 0 code_fc [7:0] sram code for fast clear. default: 0000 0000b 0x0cf fast clear and fade mode control r/w bits name description 7 - 6 fade_mode fade - in/fade - out mode select 00:left - to p c or n e r 01:right - top cor ner 10:left - bottom corner 11:right - bottom corner 5 bg_mix_en background translucent enables. 4 fg_mix_en foreground translucent enables. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 87 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 3 reserved 2 font_mix_en border/shadow translucent enable. 1 fc_mask fast clear area mask 0: sram on osd frame 1: sram on 0x0000 t o one bit font address 0 fc_en (w)/ fc_rdy i fast clear enable, when enable this bit, the hardware will fill the entire sram with the values in reg 0x0ce (code) and reg 0x0cc ~ 0x0cd (attribute). 1: enable the fast clear. if fast clear is finished, this bit fc_rdy will be clear to ?0?. 0: no effect default: 0000 0000b translucent bg = ? 001 ? bg = ? 000 ? ~ ? 1111 ? except ? 0001 ? 0x0cf 0x0a1[2:0] tp_level 0x0a1[5:3] tp_level 0x0aa[4] win_mix character b it 4 = 1 character b it 4 = 1 character background bit 5 = 1 character background except ? 0000 ? bit 5 = 1 win color win color border/shadow b it 2 = 1 border/shadow b it 2 = 1 8.13. source hsyn c digital pll control 0x0d0 hs dds pll control r/w bits name description 7 reserved 6 ver_doub_bypass vertical double buffer bypass 0: normal ( dbl_en define pll load at vs blanking or disable pll data load ) 1: bypass ( realtime pll update ) 5 d bl_en double buffer load data at vsync blanking 0: disable (ver_doub_bypass define realtime update or disable pll data load ) 1: enable 4 - 1 reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 88 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0 dds_en dds enable 0: disable 1: ensable default: 0000 0000b 0x0d1 hs frequency control r/w bits name description 6 - 4 reserved 3 hsdds_div_ctrl hs dds divide control 0: enable 1: disable 2 reserved 1 - 0 hpll_freq_range [1:0] hs dds output frequency range control 00: 100~200mhz 01: 50~100mhz 10: 25~50mhz 11: 12.5~25mhz default:0001 0000b 0x 0d2 hs pll frequency control ratio ? lo r/w bits name description 7 - 0 hsdds_ratio [7:0] hs pll frequency control ration ( for manual mode ) default: 0000 0000b 0x0d3 hs pll frequency control ratio ? mi r/w bits name description 7 - 0 hsdds_ratio [15:8] hs pll frequency control ration ( for manual mode ) default: 0000 0000b 0x0d4 hs pll frequency control ratio ? hi r/w bits name description 5 - 0 hsdds_ratio [21:16] hs pll frequency control ration ( for manual mode ) default: 000 1 000 0b 0x0 d5 hs pll pha se lock control r/w bits name description 7 - 4 reserved 3 hs_inv hsync invert 0: normal 1: inverted 2 hpll manual mode 0: auto 1: manual 1 reserved 0 hpll_en hs pll dds enable 0: disable 1: enable default: 0000 0011b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 89 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x0 d6 hs pll control r/w bits name description 7 hpll_lock_en hs pll phase lock enable 6 - 5 hpll_ploop_fit [1:0] hs pll phase lock error correction ratio 4 - 0 reserved default: 0011 1111b 0x0 d7 hs pll divider ? lo r/w bits name description 7 - 0 hsdds_divider [7:0] clock divide s value in the feedback loop of the hs pll. the hs pll reference is the input hsync signal. cr:0d1[3] must be set ?1? default: 0000 0000b 0x0 d8 hs pll divider ? hi r/w bits name description 3 - 0 hsdds_ divider [11:8] the low byte [7:0] of hs pll divider value. the register is double - buffered . divider = hsdds_ divider <11:0> + 1 f hppl = divider * f hs default: 0000 1000b 0x0 d9 hs pll phase control 1 r/w bits name description 7 - 6 clk_dly_sel select clock channel with clock delay adjusting. 00 = r 01 = g 10 = b 11 = reserved 5 - 0 hs_phase_step [5:0] hs pll 64 step phase adjust default: 1000 0000b 0x0 da hs pll phase control 2 r/w bits name description 7 - 4 reserved 3 - 0 adc_ck_delay[3:0] to adc clock delay contr ol default: 0000 0000b 0x0 db hs pll lin e count select r/w bits name description 7 - 5 reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 90 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 4 - 0 hs_line_cnt_sel[ 4:0] horizontal sync line count select ( count with 12mhz ) 00000: 2 0 line 00001: 2 1 line 00010: 2 2 line . . 11110: 2 30 line 11111: 2 31 line hs = 12m/( hs_cnt_re sult[21:0] / hs_line_cnt_sel[4:0] ) default: 0000 0100b 0x0 dc hs_dds dpll output control r/w bits name description 7 - 2 reserved 1 cap_cko_inv capture clock output polarity invert 0: normal 1: inverted 0 reserved default: 0000 0000b 0x0 dd hs hpll frequency read back ? lo r bits name description 7 - 0 hs_cnt_result [7:0] hs dpll frequency read back [7:0] hs = 12m/( hs_cnt_result[21:0] / hs_line_cnt_sel[4:0] ) default: xxxx xxxx b 0x0 de hs hpll frequency read back ? mi r bits name description 7 - 0 h s_cnt_result [15:8] hs dpll frequency read back [15:8] default: xxxx xxxx b 0x0 df hs hpll frequency read back ? hi r bits name description 5 - 0 hs_cnt_result [21:16] hs dpll frequency read back [21:16] default: xxxx xxxx b 8.14. index port access control 0x0 e0 index access port r/w bits name description 7 - 4 tbl_sel index_addr [7:0] index_addr [7:0] index_addr [7:0] index_addr [7:0] index_addr [11:0] index_addr [11:0] index_addr [11:0] table select 0000: red gamma table (read/write) (10 bits/word) 0001: green gamma table (read/write) (10 bits/word) 0010: blue gamma table (read/write) (10 bits/word) 0 011: r/g/b gamma tables modified simultaneously (write only) (10 bits/word) 0100: osd sram code only (read/write) (8 bits/word) 0101: osd sram attribute msb (read/write) (8 bits/word) 0110: osd sram attribute lsb (read/write) (8 bits/word) free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 91 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. index_addr [11:0] index_addr [11:0] index_addr [11:0] index_addr [9 :0] index_addr [7:0] index_addr [7:0] index_addr [7:0] index_addr [7:0] index_addr [7:0] 0111: osd sram a ttribute (read/write) (16 bits/word) 1000: osd sram code and attribute (read/write) (24 bits/word) 1001: osd sram code from host and attribute from reg 0x0cc ~ 0x0cd (read/write) (8 bits/word) 1010: osd programmable 1 bit color font (read/write) (24 bits/w ord) 1011: osd programmable 2 bit color font (read/write) (24 bits/word) 1100: osd programmable 4 bit color font (read/write) (24 bits/word) 1101: osd palette (read/write) (16 bits/word) 1110: hdcp data(read/write) (8 bits/word) 1111: od sdram index port a ccess 3 port_rw port read/write 0: write 1: read 2 direct_wr_gamma gamma write directly 0: write gamma table must set gamma disable 1: write gamma table directly 1 - 0 reserved default: 0000 0000b 0x0e1 index address port ? low byte r/w bits name de scription 7 - 0 index_addr [7:0] table addr ess ? low bits default: 0000 0000b 0x0e2 index address port ? high byte r/w bits name description 7 - 0 index_addr [15:8] table addr ess ? upper bits default: 0000 0000b 0x0e3 index data port r/w bits name description 7 - 0 port_data [7:0] data port for the sram, palette, and programmable font. default: 0000 0000b note: 1. if the index port?s access is over 8 bit data length, the host interface will transfer or receive data from lsb to msb. 0x0e4 ~ 0x0e5: reserved 8.15. auto gain/gauge access window control 0x0e6 auto gain/gauge window odd field vertical begin ? lo r/w bits name description 7 - 0 gi_cap_vbego [7:0] vertical capture begin for odd field. gi_cap_vbego indicates how many lines to wait after referenced edge of vsync before starting image capture. gi_cap_vbego =3, means waiting 3 lines to begin capture. this register is double - buffered. default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 92 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x0e7 auto gain/gauge window odd field vertical begin ? hi r/w bits name description 7 - 3 reserved 2 - 0 gi_cap_vbego [10:8] msb of gi_cap_vbego. this register is double - buffered. default: 0000 0000b 0x0e8 auto gain/gauge window even field vertical begin ? lo r/w bits name description 7 - 0 gi_cap_vbege [7:0] vertical capture begin for even field. gi_cap_vbege indicates how many lines to wait after referenced edge of vsync before starting image capture. gi_cap_vbege =3, means waiting 3 lines to begin capture. this register is double - buffered. default: 0000 0000b 0x0e9 auto gain/gauge window even field vertical begin ? hi r/w bits name description 2 - 0 gi_cap_vbege [10:8] msb of gi_cap_vbege. this register is double - buffered. default: 0000 0000b 0x0ea auto gain/gauge window vertical length ? lo r/w bits name description 7 - 0 gi_cap_vlen [7: 0] vertical capture length. gi_cap_vlen indicates how many lines to capture. gi_cap_vlen = 3, means capturing 3 lines. this register is double - buffered. default: 0000 0000b 0x0eb auto gain/gauge window vertical length ? hi r/w bits name description 2 - 0 gi_cap_vlen [10:8] msb of gi_cap_vlen. this register is double - buffered. default: 0000 0000b 0x0ec auto gain/gauge window horizontal begin ? lo r/w bits name description 7 - 0 gi_cap_hbeg [7:0] horizontal capture begin. gh_cap_hbeg indicates how many pixe ls to wait after referenced edge of hsync before starting image capture. gh_cap_hbeg =3, means waiting 3 pixels to begin capture. this register is double - buffered. default: 0000 0000b 0x0ed auto gain/gauge window horizontal begin ? hi r/w bits name descr iption 7 - 4 reserved 3 - 0 gi_cap_hbeg [11:8] msb of gi_cap_hbeg. this register is double - buffered. default: 0000 0000b 0x0ee auto gain/gauge window horizontal width ? lo r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 93 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name description 7 - 0 gi_cap_hwid [7:0] horizontal capture width. gi_cap_h wid indicates how many pixels to capture. gi_cap_hwid = 3, means capturing 3 pixels. this register is double - buffered. default: 0000 0000b 0x0ef auto gain/gauge window horizontal width ? hi r/w bits name description 7 - 4 reserved 3 - 0 gi_cap_hwid [11:8] msb of gi_cap_hwid. this register is double - buffered. default: 0000 0000b 8.16. display digital pll control 0x0f0 display dds pll control r/w bits name description 7 - 4 dds debug mode 3 ddds_rst display dds reset 0: normal 1: reset 2 reserved 0 ddds_e n display dds enable 0: disable 1: enable default: 0000 0000b 0x0f1 display frequency control r/w bits name description 7 - 2 reserved 1 - 0 display_port display data port control 00: dual port 01: single port default: 0001 00 00b 0x0f2 display pll frequency control ratio ? lo r/w bits name description 7 - 0 ddds_ratio [7:0] display dds frequency control ratio default: 0000 0000b 0x0f3 display pll frequency control ratio ? mi r/w bits name description 7 - 0 ddds_ratio [15:8] display dds frequency co ntrol ratio default: 0000 0000b 0x0f4 display pll frequency control ratio ? hi r/w bits name description 5 - 0 ddds_ratio [21:16] display dds frequency control ratio free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 94 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. default: 0000 1010b fout = (reference - freq ddds_ratio [21:0] ) / 2 17 fref = 12.000 mhz 0x0f5 ssc control r/w bits name description 7 - 5 ssc_mod_freq display pll spread spectrum modulation frequency control ?111? = refclk/4 ?110? = refclk/8 ?101? = refclk/16 ?100? = refclk/32 ?011? = refclk/64 ?010? = refclk/128 ?001? = refclk/256 ?000? = refclk/512 4 - 1 ssc_ratio ddds pll spread spectrum ratio ?1000? = 1/4 ?0111? = 1/8 ?0110? = 1/16 ?0101? = 1/32 ?0100? = 1/64 ?0011? = 1/128 ?0010? = 1/256 ?0001? = 1/512 ?0000? = 1/1024 0 ssc_en dds pll spread spectrum enabl e 0: disable 1: enable default: 0000 1010b 0x0f6 : reserved 0x0f7 gauge control 1 r/w bits name description 7 - 1 reserved 0 gauge_mod_sel gauge detection area mode select 0 = detecting area is defined by capture registers 1 = detecting area is defined by auto gain/gauge window registers. default: 0000 000 0b 0x0f8 gauge control 2 r /w bits name description 7 gauge_en to gauge the distribution of input data. when gauge_en set ?1?, the function is enable, then if the gauge is finished this bit is cleared to ?0?. , repeat read gauge this bit must set ?0? follow set ?1? 0 = disable 1 = enable 6 - 5 reserved 4 - 3 gauge_sel gauge source select 00: blue channel 01: green channel 10: red channel 11: reserved 2 - 0 gauge_step [7:0] the step of g auge data 000: 1 step 100: 16 step 001: 2 step 101: 32 step 010: 4 step 110: reserved 011: 8 step 111: reserved default: 0000 0000 b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 95 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x0f9 gauge result read back area select r/w bits name description 7 - 3 rese rved 2 - 0 gauge_area the gauge result read back area select 0~7 default: 0000 0 000b 0x0fa gauge offset r/w bits name description 7 - 0 gauge_offset the level of r/g/b input when gauge function is enable default: 000 0 0000b 0x0fb gauge result ? lo r bi ts name description 7 - 0 gauge_result [7:0] the gauge result of input data in capture window default: xxxx xxxxb 0x0fc gauge result ? mi r bits name description 7 - 0 gauge_result [15:8] the gauge result of input data in capture window default: xxxx xxx xb 0x0fd gauge result ? hi r bits name description 7 - 0 gauge_result [23:16] the gauge result of input data in capture window default: xxxx xxxxb 0x0fe : reserved 8.17. graphic input gauge 0x0ff accessing register page enable r/w bits name description d7 - 2 reserved d1 - 0 reg_page_sel register page enable 0 00: enable register page0. 0 01: enable register page1. 0 10: enable register page2. 0 11: enable register page3. 011: enable register page 4 . default: 0000 0000b 8.18. product id 0x1 00 product id r bits name description 7 - 4 reserved 3 - 0 chip_id chip id = 10 11 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 96 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8.19. power control 0x101 power control r/w bits name description 7 reserved 6 pu_lvdsa lvds a port power up control. 0 = power down 1 = power up 5 warm_rst chip warm reset. when warm_rs t=1, all state machines will be reset other than the all of register?s value. 0 = normal 1 = reset 4 reserved 3 gclk_off graphic port clock off. when gclk_off=1, graphic port clock is disabled to conserve power 2 vclk_off video port clock off. when vclk_off=1, video port clock is disabled to conserve power 1 reserved 0 dclk_off display clock off. when dclk_off=1, display clock is disabled to conserve power default: 0000 11 0 1b 0x102 power down control 2 r/w bits name description 7 - 6 reserved 5 pu_hpll hpll power up control. 0 = power down 1 = power up 4 reserved 3 pu_adc adc power up control. 0 = power down 1 = power up 2 reserved 1 pu_tmds tmds pd power up mode. when pu_tmds = ?0?, tmds circuit will go into power down state. 0 = pow er down 1 = power up 0 reserved default: 0000 000 0 b 0x103 ~ 0x105 : reserved 8.20. auto tune graphic auto tune control 0x106 graphic auto tune control r/w bits name description 7 gi_agpd_mod auto gain and phase detection area mode select , if this bit set ?1? then gi_auto_win don?t care . 0 = normal/ original ( depend on gi_auto_win ) 1 = detecting area is defined by auto gain/gauge window registers. ( 0x0e6 ~ 0x0ef ) free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 97 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6 - 5 gi_auto_win auto gain and phase detection area select 00 : whole frame 01 : captur e 1x : mask window 4 gi_pos_de enable position detection depending on de signal when tmds is enabled. if gi_pos_de =1, 0xff data is input to rgb channel for position detection instead of data from graphic port when de is ?1?. 3 - 2 gi_gainphs_sel [1:0] gra phic input gain and phase detection type select. 00 = phase tune 1 ( sum of difference calculate mode 1 ) 01 = phase tune 2 ( sum of difference calculate mode 2 ) 10 = min rgb gain ( read back cr:0x113 ~ 0x116 ) 11 = max rgb gain ( read back cr:0x113 ~ 0x116 ) 1 gi_gainphs_en/ gi_gainphs_rdy graphic input gain and phase detection enable. when gi_gainphs_en = 1, detection will start from next vsync. when detection is finished, this bit is cleared to ?0?. 0 = disable 1 = enable 0 gi_pos_en/ gi_pos_r dy graphic input active window position detection enable. when gi_pos_en = 1, detection will start from next vsync. when detection is finished, this bit is cleared to ?0?. 0 = disable. 1 = enable default: 0001 1100b graphic auto position 0x107 auto p osition black threshold r/w bits name description 7 - 0 gi_pos_thr [7:0] graphic data lager then gi_pos_thr will be considered to be non - black pixel for position detecting. default: 0000 1111b 0x108 auto position vertical begin for odd field ? lo r bits name description 7 - 0 gi_pos_vbego [7:0] active window vertical begin for odd field. gi_pos_vbego= 3 means there are 3 blanking lines. default: xxxx xxxx b 0x109 auto position vertical begin for odd field ? hi r bits name description 2 - 0 gi_pos_vbego [10: 8] msb of gi_pos_vbego default: xxxx xxxx b 0x10a auto position vertical begin for even field ? lo r bits name description 7 - 0 gi_pos_vbege [7:0] active window vertical begin for even field. gi_pos_vbege= 3 means there are 3 blanking lines. default: xxxx xxxx b 0x10b auto position vertical begin for even field ? hi r bits name description free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 98 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 2 - 0 gi_pos_vbege [10:8] msb of gi_pos_vbege default: xxxx xxxx b 0x10c auto position vertical length ? lo r bits name description 3 - 0 gi_pos_vlen [7:0] the active windo w vertical length. gi_pos_vlen = 3 means there are 3 active lines. default: xxxx xxxx b 0x10d auto position vertical length ? hi r bits name description 2 - 0 gi_pos_vlen [10:8] msb of gi_pos_vlen default: xxxx xxxx b 0x10e auto position horizontal begin ? l o r bits name description 7 - 0 gi_pos_hbeg [7:0] the active window horizontal begin. gi_pos_hbeg = 3 means there are 3 blanking pixels. default: xxxx xxxx b 0x10f auto position horizontal begin ? hi r bits name description 3 - 0 gi_pos_hbeg [11:8] msb of g i_pos_hbeg default: xxxx xxxx b 0x110 auto position horizontal width ? lo r bits name description 3 - 0 gi_pos_hwid [7:0] the active window horizontal width. gi_pos_hwid = 3 means there are 3 active pixels. default: xxxx xxxx b 0x111 auto position horizonta l width ? hi r bits name description 3 - 0 gi_pos_hwid [11:8] msb of gi_pos_hwid default: xxxx xxxx b graphic auto phase and gain 0x112 auto phase bit mask r/w bits name description 7 - 3 reserved 2 - 0 gi_phs_mask [2:0] decide how many lsb bits will be ma sked out, and then the difference between adjacent pixels will be added to the sum of difference accumulator. default: 0000 0100 b 0x113 auto phase sum of difference ? lo r bits name description free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 99 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. gi_phs_sdiff [7:0] auto phase sum of difference (lsb). g i_phs_sdiff specifies how the phase locking quality in adcpll block. 7 - 0 r_minmax [7:0] the minimum or maximum value of red channel data in one frame. default: xxxx xxxx b 0x114 auto phase sum of difference ? 2?nd r bits name description gi_phs_sdiff [ 15:8] second byte of gi_phs_sdiff 7 - 0 g_minmax [7:0] the minimum or maximum value of green channel data in one frame. default: xxxx xxxx b 0x115 auto phase sum of difference ? 3?rd r bits name description gi_phs_sdiff [23:16] third byte of gi_phs_sdif f 7 - 0 b_minmax [7:0] the minimum or maximum value of blue channel data in one frame. default: xxxx xxxx b 0x116 auto phase sum of difference ? hi r bits name description 7 - 0 gi_phs_sdiff [31:24] msb of gi_phs_sdiff default: xxxx xxxx b graphic auto clock 0 x117 auto clock reference width ? lo r/w bits name description 7 - 0 gi_clk_ref [7:0] auto clock reference width. this register provides the reference value for calibrating the frequency of sampling clock in adcpll block. default: 0000 0000b 0x118 auto c lock reference width ? hi r/w bits name description 7 - 4 reserved 3 - 0 gi_clk_ref [11:8] msb of auto_clk_ref default: 0000 0000b 0x119 auto clock detecting result r bits name description 7 - 6 gi_clk_comp [1:0] auto clock comparing relation. gi_clk_comp specifies the comparing relation between gi_pos_hwid and gi_clk_ref 00: gi_pos_hwid = gi_clk_ref 01: gi_pos_hwid < gi_clk_ref 1x: gi_pos_hwid > gi_clk_ref 5 - 0 gi_clk_diff difference of |gi_pos_hwid ? gi_clk_ref| free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 100 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. [5:0] the difference value is clampe d to 0x3f if difference t 0x3f default: xxxx xxxx b 0x11a : reserved video auto tune control 0x11b video auto tune control r/w bits name description 7 - 6 reserved 5 vi_auto_mask gain detection area masking when vi_gain_area = ?1? 0 = detecting area is whole frame 1 = detecting area is defined by mask window registers. ( define by cr: 0x047 ~ 0x04a ) 4 reserved 3 vi_gain_area gain detection area define enable. 0 = detecting area is over one frame except the area defined by mask window regist ers. 1 = detecting area is defined by capture registers. 2 vi_gain_sel video input gain type select 0 = min y gain 1 = max y gain 1 vi_gain_en/ vi_gain_rdy video input y min/max data detection enable. when vi_gain_en = 1, detection will start from nex t vsync. when detection is finished, this bit is cleared to ?0?. 0 = disable 1 = enable 0 vi_pos_en/ vi_pos_rdy video input active window position detection enable. when vi_pos_en = 1, detection will start from next vsync. when detection is finished, th is bit is cleared to ?0?. 0 = disable 1 = enable default: 0000 0000b video auto position 0x11c auto position black threshold r/w bits name description 7 - 0 vi_pos_thr [7:0] video data lager than vi_pos_thr will be considered to be non - black pixel for position detecting. default: 0000 1111b 0x11d auto position vertical total ? lo r bits name description 7 - 0 vi_vtotal [7:0] vertical period total. vi_vtotal =99 means total 99 lines. default: xxxx xxxx b 0x11e auto position vertical total ? hi r bits n ame description 2 - 0 vi_vtotal [10:8] msb of vi_vtotal. default: xxxx xxxx b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 101 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x11f auto position vertical begin for odd field ? lo r bits name description 7 - 0 vi_pos_vbego [7:0] active window vertical begin for odd field. vi_pos_vbego =9 means 9 blanking lines. default: xxxx xxxx b 0x120 auto position vertical begin for odd field ? hi r bits name description 2 - 0 vi_pos_vbego [10:8] msb of vi_pos_vbego. default: xxxx xxxx b 0x121 auto position vertical begin for even field ? lo r bits name description 7 - 0 vi_pos_vbege [7:0] active window vertical begin for even field. vi_pos_vbege =9 means 9 blanking lines. default: xxxx xxxx b 0x122 auto position vertical begin for even field ? hi r bits name description 2 - 0 vi_pos_vbege [10:8] msb of vi_pos_vbege. default: xxxx xxxx b 0x123 auto position vertical length ? lo r bits name description 7 - 0 vi_pos_vlen [7:0] active window vertical length. vi_pos_vlen =99 means 99 active lines. default: xxxx xxxx b 0x124 auto position vertical length ? hi r bits name description 7 - 3 reserved 2 - 0 vi_pos_vlen [10:8] msb of vi_pos_vlen. default: xxxx xxxx b 0x125 auto position horizontal total ? lo r bits name description 7 - 0 vi_htotal [7:0] horizontal period total. vi_htotal=99, means total 99 pixels. default: xxxx xxxx b 0x126 auto position horizontal total ? hi r bits name description 7 - 4 reserved 3 - 0 vi_htotal [11:8] msb of vi_htotal. default: xxxx xxxx b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 102 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x127 auto position horizontal begin ? lo r bits name description 7 - 0 vi_pos_hbeg [7:0] active window ho rizontal begin. vi_pos_hbeg =3 means 3 blanking pixels. default: xxxx xxxx b 0x128 auto position horizontal begin ? hi r bits name description 7 - 4 reserved 3 - 0 vi_pos_hbeg [11:8] msb of vi_pos_hbeg default: xxxx xxxx b 0x129 auto position horizontal wi dth ? lo r bits name description 7 - 0 vi_pos_hwid [7:0] active window horizontal width. vi_pos_hwid =99 means 99 active pixels. default: xxxx xxxx b 0x12a auto position horizontal width ? hi r bits name description 3 - 0 vi_pos_hwid [11:8] msb of vi_pos_ hwid default: xxxx xxxx b video auto gain 0x12b video min/max y value r bits name description 7 - 0 y_minmax [7:0] the minimum or maximum value of y channel data in one frame. default: xxxx xxxx b 0x12c ~ 0x12f : reserved 8.21. bright frame display registers bright frame control note ? when both bright frames are enabled and if two windows are overlapped frame2 has higher priority than frame 1. 0x130 bright frame enable control r/w bits name description 7 - 5 reserved 4 bright_ref_ctl bright frame acti ve reference 0: front (capture) 1: post (display) 3 - 2 reserved 1 bright_frm2_en enable bright frame 2 0: disable 1: enable free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 103 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0 bright_frm1_en enable bright frame 1 0: disable 1: enable default: 0000 0000b 0x131 bright frame access index select r/ w bits name description 7 - 1 reserved 0 bright_frm_sel [0] this register is used to select which frame is to be accessed or modified. it is programmed prior to accessing the registers reg 0x132 ~ 0x13b ?0? = bright frame 1 ?1? = bright frame 2 default: 0000 0000b 0x132 bright frame horizontal start ? low byte r/w bits name description 7 - 0 bright_frm_hs [7:0] bright frame horizontal start low byte [7:0]. specifies the horizontal starting position of the bright frame in pixel units. thi s register is double - buffered . default: 0000 0000b 0x133 bright frame horizontal start ? high byte r/w bits name description 7 - 4 reserved 3 - 0 bright_frm_hs [11:8] bright frame horizontal start high byte [11:8]. specifies the horizontal starting position of the bright frame in pixel units. this register is double - buffered . default: 0000 0000b 0x134 bright frame horizontal width ? low byte r/w bits name description 7 - 0 bright_frm_hw [7:0] bright frame horizontal width low byte [7:0]. spec ifies the width of the bright frame in pixel units. . this register is double - buffered . default: 0000 0000b 0x135 bright frame horizontal width ? high byte r/w bits name description 7 - 4 reserved 3 - 0 bright_frm_hw [11:8] bright frame horizontal w idth low byte [11:8]. specifies the width of the bright frame in pixel units. . this register is double - buffered . default: 0000 0000b 0x136 bright frame vertical start ? low byte r/w bits name description 7 - 0 bright_frm_vs [7:0] bright frame vert ical start low byte [7:0]. specifies the vertical starting position of the bright frame in pixel units. this register is double - buffered . default: 0000 0000b 0x137 bright frame vertical start ? high byte r/w bits name description 7 - 4 reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 104 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 3 - 0 bright_frm_vs [10:8] bright frame vertical start high byte [10:8]. specifies the vertical starting position of the bright frame in pixel units. this register is double - buffered . default: 0000 0000b 0x138 bright frame vertical height ? low byte r/w bit s name description 7 - 0 bright_frm_vh [7:0] bright frame vertical width low byte [7:0]. specifies the width of the bright frame in pixel units. . this register is double - buffered . default: 0000 0000b 0x139 bright frame vertical height ? high byte r/ w bits name description 7 - 4 reserved 2 - 0 bright_frm_vh [10:8] bright frame vertical width low byte [10:8]. specifies the width of the bright frame in pixel units. . this register is double - buffered . default: 0000 0000b 0x1 3 a ~0x142 : reserved 8.22. dvi input control 2 0x143 dvi control r/w bits name description 7 tmds_pll_pd tmds pll power down control 6 - 3 reserved 2 tmds_pwn tmds r terminal power down 1 tmds_pwn tmds g terminal power down 0 tmds_pwn tmds b terminal power down default: 0000 0000b 0x144 dvi control r/w bits name description 7 - 1 reserved 0 tmds_ipds_pd power down control of three channel impedances ( uality ct ) only for data pair , clock channel power down by 0x146.6 default: 0000 0000b 0x14 5 : reserved 0x146 dvi contr ol r/w bits name description 7 reserved 6 0: dvi clock channel power down 1: normal 5 - 0 reserved default: 1111 0011 b 0x147~0x14f : reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 105 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8.23. display port control ? display timing control ? single pixel or dual pixel output ? output signals drive curren t and slew rate control ? phase delay adjustment for accessing clock to external lcd ? dithering function supports 24 - bit quality for 18 - bit panel ? mute display control display video special mode control display general control 0x150 display control r/w bits name description 7 dp_bit_shf when display bus is 6 - bit/color, this bit enable will shift the data ra[7:2], ga[7:2], ba[7:2] to ra[5:0], ga[5:0], ba[5:0] and rb[7:2], gb[7:2], bb[7:2] to rb[5:0], gb[5:0], bb[5:0]. when display bus is 8 - bit/color, this bit enable will rotate the data ra[7:0], ga[7:0], ba[7:0] and rb[7:0], gb[7:0], bb[7:0] to right 2 bits 0 = normal 1 = shift / rotate 6 dp_lock display lock event control. under frame - sync display mode, this bit select the way of display locking to input i mage. for manual lock mode, the lock position is defined by dv_lock and dh_lock registers. 0 = manual lock 1 = auto lock 5 dp_auto display timing auto control. under frame - sync display mode, this bit select the way of display timing generation. 0 = manual 1 = auto 4 reserved 3 dp_coldep display color depth 0 = 8 - bit/color 1 = 6 - bit/color 2 dp_buswid display bus width 0 = double pixel 48 - bit 1 = single pixel 24 - bit 1 dp_de panel supports de mode 0 = panel supports sync mode, display hs/vs signal is at normal state 1 = panel supports de mode, display hs/vs signal will be pulled low 0 dp_en display enable 0 = disable 1 = enable default: 0110 0000b 0x15 1 dv_lock r/w bits name description 7 - 0 display sync manual mode v lock default: 0 000 000 0b 0x15 2 dh_lock r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 106 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name description 7 - 0 display sync manual mode h lock control low byte default: 0 000 0000b 0x15 3 dh_lock r/w bits name description 7 - 0 display sync manual mode h lock control high byte default: 0 000 0000b 0x154 display mute and color control r/w bits name description 7 - 4 dp_patt [3:0] select built - in display pattern pattern number = 0~15 if patt_bk = bank 0 0000 = gamma correction pattern 0001 = dot moir 0010 = vertical line moire (1b1w) 0011 = vertical line moire ( 2b1w) 0100 = vertical line moire (2b2w) 0101 = 256 v_gray bar 0110 = 256 h_gray bar 0111 = horizontal line moire (1b1w) 1000 = horizontal line moire (2b1w) 1001 = horizontal line moire (2b2w) 1010 = chat pattern 1011 = white pattern 11xx = rectang ular pattern, outline width is defined by xx bits. 00 = 1 pixel 01 = 3 pixels 10 = 5 pixels 11 = 7 pixels if patt_bk = bank 1 0000 = black pattern 0001~1111 = reserved 3 patt_bk built - in pattern bank select 0 = bank 0 1 = bank 1 2 cbar_en paste a cross bar on the built - in display pattern and the bar?s gray level is controlled via cbar_fg[7:0] register (0x15a) 0 = disable 1 = enable 1 - 0 dp_mute [1:0] display mute mode select 00 = normal display, rgb channel output controlled via dp_rgb 01 = mute input with output built - in display pattern, pattern color decided by dp_rgb registers. (display free - run) 1 0 = mute input with output osd and background color, background color decided by dp_bg_r/g/b registers. (display free - run) 11 = pull low al l display signals including data, clock and control lines default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 107 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x155 : reserved 0x156 display drive and polarity control r/w bits name description 7 dde_pol display de 1 = active high 0 = active low 6 dclk_pol display clock 0 = normal 1 = inverted 5 dhs_pol display hsync 1 = active high 0 = active low 4 dvs_pol display vsync 1 = active high 0 = active low 3 - 0 reserved default: 1011 0010b 0x157 display clock and data delay control r/w bits name description 7 reserved 6 - 5 dclk_ sync_sel display clock synchronous mode select 00 = display clock free - run 01 = display clock is synchronized to input(default by tcon enable) 10 = display clock free - run and disp_de synchronized to disp_clk 11 = reserved 4 - 0 dclk_dly [4:0] select panel i nterface clock delay time. (0.5ns/step) 0~32 step default: 0010 0000b 0x158 display dithering control r/w bits name description 7 - 4 dith_mode [3:0] dithering mode select 3 gamma_dith_en gamma dithering enable. ( 10 to 8 ) ( 0x1ee[2] must set ?0? ) 0 = disable 1 = enable ( gamma table set 4.0 ) , 0x390.4 set ?0? , gamma after osd 2 dith_8bit/ gamma_random rounded 10 bit gamma data output to 8 bit for dithering 0 = disable 1 = enable 8 bit dithering if gamma_dith_en = ?1? (0x158[3]), this bit is f or gamma dithering random mode control 1 dith_turbo 0 = disable 1 = enable , 0x1da[5:4] must disable 0x158[7:4] set ?0000? for check 0 dith_en dithering enable. when dith_en =0, the lsb bits of display data will be truncated if display color depth is les s than internal data resolution. 0 = disable 1 = enable default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 108 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x159 display channel select r/w bits name description 7 int_fast_en mute mode with free run timing when graphic input sync fail ( when input change hs/vs polarity , freque ncy ) 0: disable 1: enable 6 reserved 5 mute_fr_en mute mode with free run timing enable, this display horizontal sync timing reference to reg. 0x179~0x17a.( vertical free run follow display v total 0x15b,0x15c ) 0: disable 1: enable 3 reserved 2 - 0 d p_rgb [2:0] select rgb channel for display 000 = rgb normal display 001 = r channel only 010 = g channel only 011 = b channel only 100 = r & g channels 101 = r & b channels 110 = g & b channels 111 = rgb inverted display default: 0000 0000b 0x15a cross bar gray level r/w bits name description 7 - 0 cbar_fg [7:0] select the foreground gray level of cross bar for burn - in display pattern. r=g=b= 0~255 default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 109 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. active window dh_hs_wid dv_bg_beg dh_bg_wid de display background window dh_act_beg dv_vs_wid dv_act_beg dv_act_len dv_bg_len dv_bg_beg dh_total display timing control dh_act_wid dv_total figure 8.23 - 1 display timing display sync timing control 0x15b display vertical total ? lo r/w bits name description 7 - 0 dv_total [7:0] display vertical total lines. dv_total = 3 means there are 4 total lines. default: 0000 0000b 0x15c display vertical tot al ? hi r/w bits name description 2 - 0 dv_total [10:8] msb of dv_total default: 0000 0000b 0x15d display vsync pulse width r/w bits name description 7 - 0 dv_vs_wid [7:0] display vsync pulse width. dv_vs_wid =3, means pulse width is 3 lines wide. defau lt: 0000 0000b 0x15e display horizontal total ? lo r/w bits name description 7 - 0 dh_total [7:0] display horizontal total pixels. dh_total = 3 means there are 4 total pixels. default: 0000 0000b 0x15f display horizontal total ? hi r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 110 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name descriptio n 7 - 4 reserved 3 - 0 dh_total [11:8] msb of dh_total default: 0000 0000b 0x160 display hsync pulse width r/w bits name description 7 - 0 dh_hs_wid [7:0] display hsync pulse width. dh_hs_wid =3, means pulse width is 3 pixels wide. default: 0000 0000b 0 x161 r/w bits name description 7 - 2 reserved 1 dr_vupdate_en display registers update enable on next dvs when dr_vdouble_en = ?1? 0 dr_vdouble_en display registers update on next dvs enable, when this bit enable will causes display registers update on next dvs. otherwise, display registers will direct update. 0 = disable 1 = enable default: 0000 0010b display background window control 0x162 display background window vertical begin ? lo r/w bits name description 7 - 0 dv_bg_beg [7:0] display backgro und window vertical begin. dv_bg_beg indicates how many lines to wait after dvsync leading edge before starting image display. dv_bg_beg =3, means waiting 3 lines to begin display. default: 0000 0000b 0x163 display background window vertical begin ? hi r/ w bits name description 7 - 3 reserved 2 - 0 dv_bg_beg [10:8] msb of dv_bg_beg default: 0000 0000b 0x164 display background window vertical length ? lo r/w bits name description 7 - 0 dv_bg_len [7:0] display background window vertical length. dv_bg_len ind icates how many lines to display. dv_bg_len =3, means displaying 3 lines. default: 0000 0000b 0x165 display background window vertical length ? hi r/w bits name description 7 - 3 reserved 2 - 0 dv_bg_len [10:8] msb of dv_bg_len default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 111 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x166 display background window horizontal begin ? lo r/w bits name description 7 - 0 dh_bg_beg [7:0] display background window horizontal begin. dh_bg_beg indicates how many pixels to wait after dhsync leading edge before starting image display. dh_bg_beg =3, me ans waiting 3 pixels to begin display. default: 0000 0000b 0x167 display background window horizontal begin ? hi r/w bits name description 7 - 4 reserved 3 - 0 dh_bg_beg [11:8] msb of dh_bg_beg default: 0000 0000b 0x168 display background window horizont al width ? lo r/w bits name description 7 - 0 dh_bg_wid [7:0] display background window horizontal width. dv_bg_wid indicates how many pixels to display. dv_bg_wid =3, means displaying 3 pixels. default: 0000 0000b 0x169 display background window horizonta l width ? hi r/w bits name description 7 - 4 reserved 3 - 0 dh_bg_wid [11:8] msb of dh_bg_wid default: 0000 0000b 0x16a r/w bits name description 7 - 5 reserved 4 dp_port_swap a /b port swap control 0: normal 1: a/b port swap 3 dp_byte_swapb displa y bus port b byte swap control 0: normal 1: b port r/b channel byte swap 2 dp_byte_swapa display bus port a byte swap control 0: normal 1: a port r/b channel byte swap 1 dp_bit_swapb display bus port b bit swap control 0: normal 1: b port bit swa p 0 dp_bit_swapa display bus port a bit swap control 0: normal 1: port a bit swap (rgb bit7~bit0 in 8 bit mode, bit5~bit0 in 6 bit mode) default: 0000 0000b display background color control 0x16b display background color ? red r/w bits name descripti on free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 112 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7 - 0 dp_bg_r [7:0] display background window red color. default: 0000 0000b 0x16c display background color ? green r/w bits name description 7 - 0 dp_bg_g [7:0] display background window green color. default: 0000 0000b 0x16d display background colo r ? blue r/w bits name description 7 - 0 dp_bg_b [7:0] display background window blue color. default: 0000 0000b graphic display active window control 0x16e graphic display window control r/w bits name description 7 vd_en video display window enable 0 = disable 1 = enable 6 - 3 reserved 2 - 1 gd_fld [1:0] select the field to display for interlaced graphic input 00 = display both odd and even field mode 01 = display only odd field mode 10 = display only even field mode 11 = spatial interlace mode 0 gd_en graphic display window enable 0 = disable 1 = enable default: 0000 0110b 0x16f graphic display active window vertical begin ? lo r/w bits name description 7 - 0 gdv_act_beg [7:0] graphic display active window vertical begin. gdv_act_beg indicates how many lines to wait after dvsync leading edge before starting graphic image display. gdv_bg_beg =3, means waiting 3 lines to begin display. default: 0000 0000b 0x170 graphic display active window vertical begin ? hi r/w bits name description 7 - 3 rese rved 2 - 0 gdv_act_beg [10:8] msb of gdv_act_beg default: 0000 0000b 0x171 graphic display active window vertical length ? lo r/w bits name description 7 - 0 gdv_act_len [7:0] graphic display active window vertical length. gdv_act_len indicates how many lin es to display. gdv_act_len =3, means displaying 3 lines. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 113 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. default: 0000 0000b 0x172 graphic display active window vertical length ? hi r/w bits name description 7 - 3 reseerved 2 - 0 gdv_act_len [10:8] msb of gdv_act_len default: 0000 0000b 0x173 graphic display active window horizontal begin ? lo r/w bits name description 7 - 0 gdh_act_beg [7:0] graphic display active window horizontal begin. gdh_act_beg indicates how many pixels to wait after dhsync leading edge before starting graphic image display. gdh_ act_beg =3, means waiting 3 pixels to begin display. default: 0000 0000b 0x174 graphic display active window horizontal begin ? hi r/w bits name description 7 - 4 reserved 3 - 0 gdh_act_beg [11:8] msb of gdh_act_beg default: 0000 0000b 0x175 graphic displ ay active window horizontal width ? lo r/w bits name description 7 - 0 gdh_act_wid [7:0] graphic display active window horizontal width. gdh_act_wid indicates how many pixels to display. gdh_act_wid =3, means displaying 3pixels. default: 0000 0000b 0x176 graphic display active window horizontal width ? hi r/w bits name description 7 - 4 reserved 3 - 0 gdh_act_wid [11:8] msb of gdh_act_wid default: 0000 0000b 0x177 h lock r bits name description 7 - 0 lock_rd_h [7:0] lock h position read back low byte def ault: xxxx xxxx b 0x178 v lock r bits name description 7 - 4 lock_rd_v [3:0] lock v position read back 3 - 0 lock_rd_h [11:8] lock h position read back high byte default: xxxx xxxx b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 114 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. free run htotal control 0x179 free run horizontal total ? lo r/w bits name description 7 - 0 frh_total [7:0] free run horizontal total pixels. this register is used when mute_fr_en = ?1? (reg. 0x159[5]). dh_total = 3 means there are 4 total pixels. default: 0000 0000b 0x17a free run horizontal total ? hi r/w bits name description 7 - 4 reserved 3 - 0 frh_total [11:8] msb of dh_total default: 0000 0000b 0x17b~0x181 : reserved 0x182 auto control h - total read back r bits name description 7 - 0 display auto mode h total read back default: xxxx xxxx b 0x183 auto control h - total read b ack r bits name description 3 - 0 display auto mode h total read back default: xxxx xxxx b 0x184 residual display hsync control r bits name description 7 - 0 display manual mode residual hs count read back default: xxxx xxxx b 0x185 residual display hsyn c control r bits name description 7 - 0 display manual mode residual hs count read back default: xxxx xxxx b 0x186 residual display mode control r//w bits name description 7 - 0 0x00 for normal display hs/vs 0x10 for average hs , last hs cycle is same as others default: 0000 0 0000b 0x187~0x18c : reserved 0x18d residual display mode control r/w bits name description 5 internal circuit option for display manual mode , default ?0x00? default: 000 0 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 115 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. fifo over/under - flow interrupt 0x18e fifo interrup t flag r bits name description 1 int_ffov fifo over - flow interrupt flag 0 int_ffun fifo under - flow interrupt flag default: xxxx xxxx b 0x18e fifo interrupt flag clear w bits name description 1 clr_ffov writing ?1? will clear int_ffov flag 0 clr_ffun writing ?1? will clear int_ffun flag default: 0000 0000b 0x18f fifo interrupt enable r/w bits name description 7 - 2 reserved 1 int_ffov_en fifo over - flow interrupt enable 0 int_ffun_en fifo under - flow interrupt enable default: 0000 0000b 0x190 : res erved 0x191 fifo control r/w bits name description 7 bp_vi bypass the vi ( vertical interpolation ) data and power down the clock for up scaling 6 bp_hi bypass the hi ( horizontal interpolation ) data and power down the clock for up scaling 5 bp_srg b bypass the srgb data and power down the clock 4 bp_vc bypass the vc ( vertical compression ) data and power down the clock for down scaling 3 bp_hc bypass the hc ( horizontal compression ) data and power down the clock for down scaling 2 gr_auto_clk f ifo reference clock control auto select enable 0 = disable 1 = enable 1 - 0 gr_fifo_clk_sel [1:0] fifo reference clock control source select 00 = graphic clock 01 = video clock default: 0000 0100b 0x192 ~ 0x195 : reserved 8.24. sync processor ? h/v sync freque ncy counter & polarity detection ? h/v sync frequency change detection ? composite/separate auto - switch ? interlaced/progressive input detection ? programmable free - run h/v frequency ? status change interrupt free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 116 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. graphic sync processor control 0x196 graphic sync proce ssor control 1 r/w bits name description 7 dvi_sync_sel select the sync input source when dvi interface is enabled. 0 = from dvi de signal 1 = from dvi hs/vs signal 6 hpll_hs_inv invert the hpll output hs polarity 0 = normal 1 = invert 5 - 4 gi_hs_sr c [1:0] select the hsync input source to sync processor and core logic. 00 = hpll_hs - > sync processor and core logic 01 = raw_hs - > sync processor and core logic 10 = raw_hs - > sync processor and hpll_hs - > core logic 11 = sog_hs - > sync processor and core logic 3 - 2 gi_vcnt_bit [1:0] select the bit number of gi_vcnt. 00 = 11 - bit. overflow freq = 27.32hz 01 = 12 - bit. overflow freq = 13.66hz 1x = 13 - bit. overflow freq = 6.83hz 1 - 0 gi_sync_type [1:0] graphic sync type select. 00 = separate sync 01 = composite sync 1x = reserved default: 0001 0110b 0x197 graphic sync processor control 2 r/w bits name description 7 - 6 reserved 5 gi_vrun_en vsync output free run enable 0 = disable 1 = enable 4 gi_hrun_en hsync output free run enable 0 = disab le 1 = enable 3 gi_vso_pol vsync output polarity control 0 = active low 1 = active high 2 gi_hso_pol hsync output polarity control 0 = active low 1 = active high 1 int_vso _en internal vs output pin - 113 enable 0 = enable 1 = disable 0 int_hso _e n internal hs output pin - 114 enable 0 = enable 1 = disable default: 1000 1111b interlace detector control 0x198 graphic field decision window r/w bits name description free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 117 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7 - 4 gi_fld_winedn [3:0] define the end position of graphic field decision window. 3 - 0 gi_fld_winbeg [3:0] the g_hs period is divided into 16 segments; a field decision window is defined by gi_fld_winbeg and gi_fld_winend. gi_fld_winbeg defines the window begin position, and gi_fld_winend defines the end position. if the g_vs reference edge locates inside the window, it means odd field. default: 0100 1100b 0x199 graphic sync processor control 3 r/w bits name description 7 - 2 reserved 1 gi_fld_edge select the reference edge of vsync in graphic field detector 0 = leading edge 1 = tra iling edge 0 gi_fld_inv invert the polarity of graphic field detector output signal from sync processor 0 = normal 1 = invert default: 0000 0000b sync status 0x19a graphic sync processor status r bits name description 7 gi_vcnt_ov gi_vcnt overflow f lag 0 = non - overflow 1 = overflow 6 gi_hcnt_ov gi_hcnt overflow flag 0 = non - overflow 1 = overflow 5 gi_cspre composite sync present flag 0 = non - present 1 = present 4 gi_vpre vsync present flag 0 = non - present 1 = present 3 gi_hpre hsync prese nt flag 0 = non - present 1 = present 2 gi_inte interlace input detected flag 0 = progressive input 1 = interlaced input 1 gi_vpol vsync polarity 0 = active low 1 = active high 0 gi_hpol hsync polarity 0 = active low 1 = active high default: xxxx xxxx b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 118 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. h/v sync counter 0x19b graphic hsync counter ? lo r bits name description 7 - 0 gi_hcnt [7:0] hsync period counter. gi_hcnt is the number of clock (=refclk/4) in the period of 32x hsync. hfreq = (refclk x 32)/(4 x gi_hcnt) hz default: xxxx xxxx b 0x 19c graphic hsync counter ? hi r bits name description 4 - 0 gi_hcnt [12:8] msb of gi_hcnt default: xxxx xxxx b 0x19d graphic vsync counter ? lo r bits name description 7 - 0 gi_vcnt [7:0] vsync period counter. gi_vcnt is a 12 - bit counter; counter value is the number of clock (=refclk/256) between two vsync pulses. vfreq = refclk/(256 x gi_vcnt) default: xxxx xxxx b 0x19e graphic vsync counter ? hi r bits name description 4 - 0 gi_vcnt [12:8] msb of gi_vcnt. default: xxxx xxxx b h/v free run divider 0x19f hs o free run divider ? lo r/w bits name description 7 - 0 hfree_div [7:0] hsync output to sync processor free - run divider value. hsync pulse width = 15x refclk hfreq (free - run) = refclk/(hfree_div+1) 0~511 default: 0010 0111b 0x1a0 hso free run divider ? hi r /w bits name description 7 - 1 reserved 0 hfree_div [8] msb of hfree_div default: 0000 0001b 0x1a1 vso free run divider ? lo r/w bits name description 7 - 0 vfree_div [7:0] vsync output to sync processor free - run divider value. vsync pulse width = 3x h free vfreq (free - run) = hfreq (free - run)/ (vfree_div+1) 0~2048 default: 0010 0110b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 119 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x1a2 vso free run divider ? hi r/w bits name description 7 - 3 reserved 2 - 0 vfree_div [10:8] msb of vfree_div default: 0000 0011b h/v present threshold 0x1a3 hsync pre sent low count threshold r/w bits name description 7 reserved 6 - 0 hpre_thr_lo [6:0] hsync non - present counter threshold 1 (0h)~127 (7eh) not - present when hfreq < refclk / (4 x 8192 x hpre_thr_lo) hz default: 0010 1101b 0x1a4 hsync present high count threshold r/w bits name description 7 reserved 6 - 0 hpre_thr_hi [6:0] hsync present counter threshold 1 (0h)~127 (7eh) present when hfreq > refclk / (4 x 8x hpre_thr_hi) hz default: 0010 1100b 0x1a5 vsync present low count threshold r/w bits name de scription 7 reserved 6 - 0 vpre_thr_lo [6:0] vsync non - present counter threshold 1 (0h)~127 (7eh) not - present when vfreq < refclk / (4 x 8192 x vpre_thr_lo) hz default: 0010 1100b 0x1a6 vsync present high count threshold r/w bits name description 7 r eserved 6 - 0 vpre_thr_hi [6:0] vsync present counter threshold 1 (0h)~127 (7eh) present when vfreq > refclk / (4 x 2048x vpre_thr_hi) hz default: 0010 1100b h/v frequency change threshold 0x1a7 hsync freq change threshold r/w bits name description 7 - 0 hcnt_thr [7:0] hsync counter value change threshold for mode change detection. 1~256 default: 0000 0000b 0x1a8 vsync freq change threshold r/w bits name description 7 - 5 h_chang_cnt the int_hfreq will occur if the times out of hsync frequency change free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 120 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. tim e are more than chang_cnt setting. 000~111: 1, 4, 8, ~ 28 times 4 - 0 vcnt_thr [4:0] vsync counter value change threshold for mode change detection. 1~32 default: 0000 0000b interrupt control 0x1a9 sync interrupt enable 1 r/w bits name description 7 int_ inv invert the polarity of irqn output signal 0 = normal 1 = invert 5 int_vfreq_en vsync frequency change interrupt enable 0 = disable 1 = enable 4 int_hfreq_en hsync frequency change interrupt enable 0 = disable 1 = enable 3 int_vpol_en vsync pol arity change interrupt enable 0 = disable 1 = enable 2 int_hpol_en hsync polarity change interrupt enable 0 = disable 1 = enable 1 int_vedge_en vsync rising edge occur interrupt enable 0 = disable 1 = enable 0 int_hedge_en hsync rising edge occur interrupt enable 0 = disable 1 = enable default: 1000 0000b 0x1aa sync interrupt enable 2 r/w bits name description 7 - 5 reserved 4 int_dvipre_en dvi sync present or non - present interrupt enable 0 = disable 1 = enable 3 int_ispre_en interlaced syn c present or non - present interrupt enable 0 = disable 1 = enable 2 int_cspre_en composite sync present or non - present interrupt enable 0 = disable 1 = enable 1 int_vpre_en vsync present or non - present interrupt enable 0 = disable 1 = enable 0 int_ hpre_en hsync present or non - present interrupt enable 0 = disable 1 = enable default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 121 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x1ab sync interrupt flag 1 r bits name description 5 int_vfreq vsync frequency change interrupt 4 int_hfreq hsync frequency change interrupt 3 int_vp ol vsync polarity change interrupt 2 int_hpol hsync polarity change interrupt 1 int_vedge vsync rising edge occur interrupt 0 int_hedge hsync rising edge occur interrupt default: xxxx xxxx b 0x1ac sync interrupt flag 2 r bits name description 4 int _dvipre dvi sync present or non - present interrupt 3 int_ispre interlaced sync present or non - present interrupt 2 int_cspre composite sync present or non - present interrupt 1 int_vpre vsync present or non - present interrupt 0 int_hpre hsync present or non - present interrupt default: xxxx xxxx b 0x1ab sync interrupt flag 1 clear w bits name description 7 - 6 reserved 5 clr_vfreq writing ?1? will clear int_vfreq flag 4 clr_hfreq writing ?1? will clear int_hfreq flag 3 clr_vpol writing ?1? will clear in t_vpol flag 2 clr_hpol writing ?1? will clear int_hpol flag 1 clr_vedge writing ?1? will clear int_vedge flag 0 clr_hedge writing ?1? will clear int_hedge flag default: 0111 1111b 0x1ac sync interrupt flag 2 clear w bits name description 7 - 5 reserve d 4 clr_dvipre writing ?1? will clear int_dvipre flag 3 clr_ispre writing ?1? will clear int_ispre flag 2 clr_cspre writing ?1? will clear int_cspre flag 1 clr_vpre writing ?1? will clear int_vpre flag 0 clr_hpre writing ?1? will clear int_hpre flag default: 0000 0 0 00 b 0x1ad dvi sync status r bits name description 7 - 2 reserved 1 dvi_depol dvi de polarity. 0 = active low 1 = active high 0 dvi_scdt dvi sync detect. 0 = when de is inactively, indicating the link is down 1 = when de is actively toggling indicating that the link is alive. the scdt output itself, however, remains in the active mode at all times. free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 122 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. default: xxxx xxxx b video sync processor control 0x1ae video sync processor status r bits name description 2 vi_inte interlace input de tected flag 0 = progressive input 1 = interlaced input 1 vi_vpol vsync polarity 0 = active low 1 = active high 0 vi_hpol hsync polarity 0 = active low 1 = active high default: xxxx xxxx b 0x1af hs auto de - bouncing r/w bits name description 7 v_fr ont_bounce read - back v front status 0: no bouncing happen 1: bouncing happen at v front porch , write ?1? to clear this flag 6 v_back_bounce read - back v back status 0: no bouncing happen 1: bouncing happen at v back porch , write ?1? to clear this flag 5 debounce_del de - bounce manual mode delay enable 0: disable 1: enable 4 debounce_auto 0: de - bounce auto mode 1: de - bounce manual mode 3 reserved 2 debounce_en de - bounce enable 1 reserved 0 comp_h_ins composite h insertion mode default: 0 0 00 1100b 0x1b0 field polarity control r/w bits name description 7 - 1 reserved 0 vi_fld_inv invert the polarity of video field detector output signal 0 = normal 1 = invert default: 0000 0000 b 0x1b1 hsync pulse width counter r/w bits name description 7 - 0 gi_ hs_wid [7:0] hsync pulse width counter. gi_hs_wid is the number of refclk in the period of hsync. hpswid = (1/refclk x gi_hs_wid) default: 0 11 0 010 0b 0x1b2 vsync pulse width counter r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 123 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name description 7 - 0 gi_vs_wid [7:0] vsync pulse width counter . gi_vs_wid is the number of clock in the period of hsync. default: 0000 00 0 0b 0x1b3 r/w bits name description 7 - 0 pre_coast sets the number of hsync periods that coast becomes active prior to vsync to separate input composite sync default: 0000 000 0b 0x1b4 r/w bits name description 7 - 0 pos_coast sets the number of hsync periods that coast stays active following vsync to separate input composite sync default: 0000 0000b 0x1b5 graphic v t otal counter - lo r bits name description 7 - 0 gi_vtotal [7: 0] vertical total counter. gi_vtotal is an 11 - bit counter, counter value is the number of hsync between two vsync pulses. default: xxxx xxxx b 0x1b6 graphic v t otal counter - hi r bits name description 2 - 0 gi_vtotal [10:8] msb of gi_vtotal default: xxxx x xxx b 0x1b7 : reserved 8.25. lvds output control 0x1b8 lvds output control r/w bits name description 7 lvds_pol_swap lvds channel polarity swap (positive/negative) 0 = normal 1 = enable 6 lvds_ch_swap lvds channel swap 0 = normal 1 = enable, when enable, t 0/t3 swap, tclk1/t1 swap, t4/t7 swap, tclk2/t5 swap 5 - 3 lvds_level [2:0] fine tune lvds output differential voltage 000: standard output 200 mvp - p 001: output 250 mvp - p 010: output 300 mvp - p 011: output 450 mvp - p 100~111: reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 124 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 2 - 1 lvds_ico [1:0] char ge pump current 00 : 60ua 01 : 100ua 10 : 200ua 11 : 320ua 0 lvds_rfb data strobe edge selection 0 = falling edge strobe 1 = rising edge strobe default: 0000 0000b 0x1b9 display output interface control r/w bits name description 7 - 2 reserved 1 dos_ sel display output interface selection when timing controller disable 0 = lvds 0 reserved default: 0001 0000b 0x1ba : reserved 0x1b b auto offset control - 1 r /w bits name description 7 ao_satu_pretect auto offset saturation protect ( for clamp 0v mode only ) 0: disable ( for y p bpr mode ) 1: enable ( for rgb mode ) 6 - 5 reserved 4 - 0 calcul_period define the period of data calculation that start from falling edge of clamp pulse + 8t s et ? 1 ? mean is 1x8+7=15 pixel be calculated for auto offset default : 0000 0000b 0x1bc auto offset control - 2 r/w bits name description 7 ao_line_mode_rdy auto offset line mode ready, when detection is finished, this bit is set to ?1? 6 ao_line_mode auto offset line mode enable 0 = disable 1 = enable 5 - 1 reserved 1 default ?1? for auto offset enable 0 ao_en auto offset enable 0 = disable 1 = enable default: 0000 0000b 0x1bd auto offset target value of red channel r/w bits name description 7 - 0 ao_rvalue default: 0000 0000b 0x1be auto offset target value of green channel r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 125 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name description 7 - 0 ao_gvalue default: 0000 0000b 0x1bf auto offset target value of blue channel r/w bits name description 7 - 0 ao_rvalue default: 0000 0000b 0x1c0 auto offset adjust value ? red channel r bits name descript ion 7 - 0 ao_adj_rvalue default: 0000 0000b 0x1c1 auto offset adjust value ? green channel r bits name description 7 - 0 ao_adj_gvalue default: 0000 0000b 0x1c2 auto offset adjust value ? blue channel r bits name description 7 - 0 ao_adj_rvalue defaul t: 0000 0000b 0x1c3 auto offset mid value read back ? red channel r bits name description 7 - 0 ao_mid_rvalue default: 0000 0000b 0x1c4 auto offset mid value read back ? green channel r bits name description 7 - 0 ao_mid_gvalue default: 0000 0000b 0x1c 5 auto offset mid value read back ? blue channel r bits name description 7 - 0 ao_mid_rvalue default: 0000 0000b 0x1c6~0x1cb : reserved 0x1cc asynchronous random dithering control r/w bits name description 7 - 3 reserved 2 dp_ard_en display asynchronou s random dithering enable 0x1da.4 or 0x1da.5 must enable 1 ga_ard_en gamma asynchronous random dithering enable 0x158.2 set ?1? 0 srgb_ard_en srgb asynchronous random dithering enable default: 0000 0000b 0x1cd~0x1cf : reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 126 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8.26. srgb control 0x1d0 srgb co ntrol r/w bits name description 7 bf_srgb_en bright frame srgb enable 6 srgb_tbl_sel srgb access select 0: normal srgb 1: bright frame srgb 5 srgb_dith_en srgb dithering enable , 0x1d0.0 must set ?1? 4 random_dith_en 0: static dithering enable 1: random dithering enable 3 srgb_force_upd force update srgb 0: disable 1: force update the srgb coefficient to h/w , if 0x161[1:0] set ?11? then these srgb register update on next dvs 2 - 1 srgb_bk_sel select srgb 3x3 matrix row bank 00 = row1 01 = r ow2 10 = row3 11 = reserved 0 srgb_en srgb enable 0: disable 1: enable default: 0000 1000b 0x1d1 srgb transfer coefficient r channel ? lo r/w bits name description 7 - 0 srgb_colum_1 [7:0] srgb 3x3 matrix column 1 coefficient lsb - 1024 ~ 1023 defaul t: 0000 0000b 0x1d2 srgb transfer coefficient r channel ? hi r/w bits name description 2 - 0 srgb_colum_1 [10:8] srgb 3x3 matrix column 1 coefficient msb default: 0000 0001b 0x1d3 srgb transfer coefficient g channel ? lo r/w bits name description 7 - 0 s rgb_colum_2 [7:0] srgb 3x3 matrix column 2 coefficient lsb - 1024 ~ 1023 default: 0000 0000b 0x1d4 srgb transfer coefficient g channel ? hi r/w bits name description 2 - 0 srgb_colum_2 [10:8] srgb 3x3 matrix column 2 coefficient msb default: 0000 0000b 0x1d5 srgb transfer coefficient b channel ? lo r/w bits name description free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 127 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7 - 0 srgb_colum_3 [7:0] srgb 3x3 matrix column 3 coefficient lsb - 1024 ~ 1023 default: 0000 0000b 0x1d6 srgb transfer coefficient b channel ? hi r/w bits name description 2 - 0 sr gb_colum_3 [10:8] srgb 3x3 matrix column 3 coefficient msb default: 0000 0000b 0x1d7 srgb offset coefficient r/w bits name description 7 - 0 srgb_coef_offset [7:0] the offset coefficient of srgb matrix - 7f ~ 7f default: 1000 0000b 0x1d8 srgb dithering control 1 r/w bits name description 7 random_rst display random dither reset mode ( 0x1ed[4] must set ?1? ) 0: disabel 1: enable 6 reserved 5 - 4 dith_10 ?10? dithering type , 0x1d0.4 must set ?0? 3 reserved 2 - 0 dith_01 ?01? dithering type , 0x1d0 .4 must set ?0? default: 0000 0000b 0x1d9 : reserved 0x1da display random dithering control r/w bits name description 7 reserved 6 rst _period r andom reset period setting 0 = 1 frame 1 = if dith_turbo (reg. 0x158[1]) set to ?1?, the period is 4 frame else the period is 16 frame 5 mix_dith_en display mix mode dithering enable 0: disable 1: enable 4 random_en random dithering mode enable 3 - 2 static_cnt static dithering active period counter 0x1da.5 must enable 1 - 0 random_cnt random dithering active period counter 0x1da.5 must enable default: 0000 0111b 0x1db gamma dithering control r/w bits name description 7 - 6 reserved 5 - 4 dith_10 ?10? dithering type , 0x158.2 must set ?0? , 0x1db.7 set ?0? 3 reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 128 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 2 - 0 dith_01 ?01? dithering type , 0x15 8.2 must set ?0? , 0x1db.7 set ?0? default: 0000 0000b 0x1dc ~ 0x1e5 : reserved 0x1e6 adc test mode control r/w bits name description 7 internal ldo 0: 1.8v ( resistor ) 1: 1.6v ( bandgap ) 6 reserved 5 internal ldo 0: 1.8v ( resistor ) 1: 1.6v ( b andgap ) 4 - 1 reserved 0 rstb reset adc data to low 0: reset 1: normal default 0 00 0 000 1b 0x1e7 hpll ldo r/w bits name description 7 - 2 reserved 1 hpll _ldo hpll ldo 0: 1.8v ( bandgap ) 1: 1.6v ( resistor ) 0 page3_option page 3 function option 0: hdcp control 1: dvi auto equalize default 0100 00 00 b 0x1e8 ~ 0x1ec : reserved 0x 1ed adc power cotrol r/w bits name description 7 reserved 6 adc_bias[3] adc op bios select msb , 0x1f1 for lsb 5 bw[3] adc bandwidth msb 3 bg_sel adc bios 0: reseistor 1: bandgap 2 - 0 reserved default 0000 0000 b 0x1ee power down control r/w bits name description 7 reserved 6 bf_pwn bf bypass for power down 5 osd_pwn osd bypass for power down 4 gamma_pwn gamma bypass for power down 3 dis_dither_pwn display dither bypass for power down free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 129 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 2 gamma_dither_pwn gamma dither bypass for power down 1 reserved 0 srgb_pwn srgb bypass for power down default ? 0000 0010b 0x1ef lvds control r/w bits name description 7 - 3 reserved 2 lvds _pwr 0: lvds off 1: lvds on 1 - 0 reserved default ? 0000 0100 b 0x1f0 : reserved 0x1f1 adc control r/w bits name description 7 - 6 reserved 5 - 4 radc_bias[1:0] radc op bios se lect 3 - 2 gadc_bias[1:0] radc op bios select 1 - 0 badc_bias[1:0] radc op bios select default ? 00 11 1111 b 0x1f2 ~ 0x1f3 : reserved 0x1f4 lvds control r/w bits name description 7 - 0 lvds internal circuit control option default ? 1 000 00 1 0b 0x1f5 lvds cont rol r/w bits name description 7 reserved 6 lvds_offset lvds offset voltage source 0: band gap 1: resistor 5 reserved 4 pull_low lvds output power down buffer control 0: pull low output 1: tri - state output 3 - 0 for internal circuit option default ? 000 0 0000b 0x1f6 lvds control r/w bits name description 7 - 0 lvds internal circuit control option default ? 0000 0000b 0x1f7 lvds control r/w bits name description free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 130 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7 pd_lv1 lvds port a power control 0: power down 1: power up 6 pd_lv2 lvds port b power control 0: power down 1: power up 5 - 0 reserved default ? 0010 0010 b 0x1f8 ~ 0x1f9 : reserved 0x1fa lvds control r/w bits name description 7 lvds internal circuit control option default ? 00 0 0 00 0 0b 0x1fb ~ 0x1fe : reserved 0x1ff accessing register p age enable r/w bits name description 7 - 2 reserved 1 - 0 reg_page_sel register page enable 0 00: enable register page0. 0 01: enable register page1. 0 10: enable register page2. 0 11: enable register page3. 100 : enable register page 4 . default: 0000 0 000b 0x200 ~ 0x2fe : reserved 0x2ff accessing register page enable r/w bits name description 7 - 2 reserved 1 - 0 reg_page_sel register page enable 0 00: enable register page0. 0 01: enable register page1. 0 10: enable register page2. 0 11: enable reg ister page3. 100 : enable register page 4 . default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 131 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8.27. high - bandwidth digital content protection system hdcp index port access control see section 9.14 index port access control hdcp control register map address r/w register name description 0x300 ~ 0x301 ~ 0x302 ~ 0x303 ~ 0x304 r bksv[7:0] bksv[15:8] bksv[23:16] bksv[31:24] bksv[39:32] for transmitter read only video receiver ksv. this value must always be available for reading, and may be used to determine that the video receiver is hdcp ca pable. valid ksvs contain 20 ones and 20 zeros, a characteristic that must be verified by video transmitter hardware before encryption is enable. 0x305 ~ 0x307 r reserved reserved all bytes read as 0x00 0x308 ~ 0x309 r ri?[7:0] ri?[15:8] for transmitter read only link verification response. updated every 128 th frame. it is recommended that graphics systems protect against errors in the i2c transmission by reading this value when unexpected values are received. this value must be available at all times be tween updates. r0? must be available a maximum of 100ms after aksv is received. subsequent ri? values must be available a maximum of free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 132 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 128 pixel clocks following the assertion of ctl3 0x30a r pj? for transmitter read only ( for hdcp v1.1 ) enhanced link ver ification response. updated upon receipt of first video pixel received when frame counter value (j mod 16) == 0. the value is the xor of the decrypted byte on channel zero of the first video pixel with the least significant byte of rj. rj is derived from t he output function in the same manner as ri, but is captured every 16 th counted frame (rather than every 128 th counted frame). 0x30b~0x30f r reserved reserved all bytes read as 0x00 0x310 ~ 0x311 ~ 0x312 ~ 0x313 ~ 0x314 r aksv[7:0] aksv[15:8] aksv[23:16] aksv[31:24] aksv[39:32] for transmitter write only hdcp transmitter ksv. writes to this multi - byte value are written least significant byte first. the final write to 0x14 triggers the authentication sequence in the hdcp receiver, and the current ainfo val ue is copied from the port, takes effect, and the port is reset to the default value of zero. 0x315 r ainfo for transmitter write only bits 7 - 2: reserved zeros. bit 1: enable_1.1_features. this bit enables the advance cipher option. if in dvi mode, it als o enables the enhanced encryption status signaling (eess) (in hdmi mode, eess is enabled regardless of this bit setting). this bit resets to default zero when the hdcp receiver becomes attached or active, or is reset, or the last byte of aksv is written. a write to the last byte of aksv copies the port value and causes it to take effect, and then resets the port value to the default value of zero. thus the options must be explicitly enabled prior to each authentication. bit 0: reserved (must be zero). 0x3 16 ~0x317 r reserved reserved all bytes read as 0x00 0x318 ~ 0x319 ~ 0x31a ~ 0x31b ~ 0x31c ~ 0x31d ~ 0x31e ~ 0x31f r an[7:0] an[15:8] an[23:16] an[31:24] an[39:32] an[47:40] an[55:48] an[63:56] for transmitter write only session random number. this mu lti - byte value must be written by the hdcp transmitter before the ksv is written. 0x320~0x33f reserved 0x340 w bcaps for transmitter read only bit 7 - 5: reserved bit 4: fast. when set to one, this device supports 400 khz transfers. when zero, 100 khz is the maximum transfer rate supported. note that 400khz transfers are not permitted to any device unless all devices on the i2c bus are capable of 400khz transfer. the transmitter may not be able to determine if the edid rom, present on the hdcp rece iver, is capable of 400khz operation. this bit does not change while the hdcp receiver is active. bits 3 - 2: reserved (must be zero). bit 1: 1.1_features. when set to one, this hdcp receiver supports enhanced free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 133 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. encryption status signaling (eess), advance cipher, and enhanced link verification options. for the hdmi protocol, enhanced encryption status signaling (eess) capability is assumed regardless of this bit setting. this bit does not change while the hdcp receiver is active. bit 0: fast_reauthenticati on. when set to 1, the receiver is capable of receiving (unencrypted) video signal during the session re - authentication. all hdmi - capable receivers shall be capable of performing the fast re - authentication even if this bit is not set. this bit does n ot change while the hdcp receiver is active. default: 8?h11 0x341 ~ 0x342 reserved 0x343 r ri? frame count frame count status for ri? update default: 8?h00 0x344 r frame pj? pj? value for every frame default: 8?h00 0x345 r frame ri?(l) ri? low byte value for every frame default: 8?h00 0x346 r frame ri?(h) ri? high byte value for every frame default: 8?h00 0x347 r misc ctrl status bit 7~ 4: frame count status for pj? update bit 3: authentication ok bit 2: km calculation finished bit 1: aksv bytes ar e all received bit 0: ainfo in effect default: 8?h00 0x348 r mi? byte0 mi? byte0 value for every frame default: 8?h00 0x349 r mi? byte1 mi? byte1 value for every frame default: 8?h00 0x34a r mi? byte2 mi? byte2 value for every frame default: 8?h00 0x34 b r mi? byte3 mi? byte3 value for every frame default: 8?h00 0x34c r mi? byte4 mi? byte4 value for every frame default: 8?h00 0x34d r mi? byte5 mi? byte5 value for every frame default: 8?h00 0x34e r mi? byte6 mi? byte6 value for every frame default: 8?h 00 0x34f r mi? byte7 mi? byte7 value for every frame default: 8?h00 0x350 r ks? byte0 ks? byte0 value of session key default: 8?h00 0x351 r ks? byte1 ks? byte1 value of session key default: 8?h00 0x352 r ks? byte2 ks? byte2 value of session key default : 8?h00 free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 134 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x353 r ks? byte3 ks? byte3 value of session key default: 8?h00 0x354 r ks? byte4 ks? byte4 value of session key default: 8?h00 0x355 r ks? byte5 ks? byte5 value of session key default: 8?h00 0x356 r ks? byte6 ks? byte6 value of session key def ault: 8?h00 0x357 r ki? byte0 ki? byte0 for every frame default: 8?h00 0x358 r ki? byte1 ki? byte1 for every frame default: 8?h00 0x359 r ki? byte2 ki? byte2 for every frame default: 8?h00 0x35a r ki? byte3 ki? byte3 for every frame default: 8?h00 0x3 5b r ki? byte4 ki? byte4 for every frame default: 8?h00 0x35c r ki? byte5 ki? byte5 for every frame default: 8?h00 0x35d r ki? byte6 ki? byte6 for every frame default: 8?h00 0x35e r/w authentication built in self test stat us bit 7: self test done ( read status ) bit 6: bist is working ( read status ) bit 5: r0? fault bit 4: m0? fault bit 3: ks? fault bit 2: km? fault bit 1: self test fault happens due to bit5~bit2 faults bit 0: authentication bist enable ( use internal 2 test keys ) default: 8?h00 0x3 5f r/w key set pair select for authentication built in self test bit7~bit2: reserved bit1~0: ( for self test ) 00: a1 - b1 key pair 01: a1 - b2 key pair 10: a2 - b1 key pair 11: a2 - b2 key pair default: 8?h00 0x360 r/w hdcp input control bit 7: hdcp clk input fr om 1: ref clk ( for start up load key to hdcp address from eeprom ) 0: pixel clk(tmds) for normal operate bit 6: hdcp clk input invert mode ( tmds clk ) 1: clk inverted 0: clk non - inverted bit 5~3: hdcp input de pipe delay selection 000: no delay 001: 1t delay 010: 2t delay 011: 3t delay 100: 4t delay others: 5t delay free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 135 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bit 2~0: hdcp input data pipe delay selection 000: no delay 001: 1t delay 010: 2t delay 011: 3t delay 100: 4t delay others: 5t delay default: 8?h80 0x361 r/w hdcp input sync selection bit 7 ~4: reserved bit 3 : hdcp key set decryption ( for key set decode that from eeprom ) bit 2 : reserved bit 1 : v sync selection from separated sync or decomposed sync 1: decomposed sync ( for de mode ) 0: separated sync bit 0 : h sync selection from separat ed sync or decomposed sync 1: decomposed sync 0: separated sync default : 8?h00 0x362 r sram status0 bit7~0: sram address[7:0] for sram access ( for debug only) default: 8?h00 0x363 r sram_status1 bit0: sram address[8] for sram access (for debug only) b it1: sram arbitration (for debug only) 1: servicing for hdcp cipher machine request 0: servicing for mcu read/write request ( for initial hdcp ) default: 8?h00 0x364 r/w ri update frame count bit7:0 for every this (ri_update_frame_count+1) value is reach ed, the ri value will be updated for constantly link check, for example, if 127 is set, then for every 128 th frame count, the ri value will be updated default : 8?h7f 0x365~0x367 r reserved 0x368 r/w hdcp slave address bit7~1: hdcp slave address on ddc i2c bus bit0 : hdcp reset , 0: normal , 1: reset defaut: 0x74 0x369 r hdcp status bit 7: tmds control status bit 3 ( read tmds control bit ) bit 6: tmds control status bit 2 bit 5: tmds control status bit 1 bit 4: tmds control status bit 0 bit 3: hdcp e nable 1: hdcp clock enable 0: hdcp clock disable ( for power down ) bit 2: hdcp interrupt enable 1: interrupt enable while receiver first authentication ready . 0: interrupt disable bit 1: authentication done flag , write ?1? to this bit will clear this fl ag to 0 bit 0: aksv transfer done flag , write ?1? to this but will clear this flag to 0 default: 8?h00 0x36a r/w window of bit 7~0: low byte of window of opportunity lower bound for eess free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 136 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. opportunity lower bound ( eess valid window start ) receive tmds control bit 3 ~ 0 at 512 th ~ 528 th pixel from vs start edge , if this code is ?1001? then indicate this frame is encrypted . default: 8?h00 0x36b r/w window of opportunity lower bound bit 7~0: high byte of window of opportunity lower bound for eess defau lt: 8?h02 0x36c r/w window of opportunity upper bound bit 7~0: low byte of window of opportunity upper bound for eess ( eess valid window end ) default: 8?h10 0x36d r/w window of opportunity upper bound bit 7~0: high byte of window of opportunity upper b ound for eess default: 8?h02 0x306 dvi auto equalize - 1 r/w bits name description 7 - 2 reserved 1 - 0 dvi_auto_ch_sel detect channel setecl , 0x1e7.0 must set ?1? and read - back from 0x317 ~ 0x31b 00 : bl ue 01 : green 10 : red default: 0000 0000b 0x 308 dvi auto equalize - 2 r bits name description 7 - 3 reserved 2 for r uality , read - back data if ?1? indicate input data decode maybe is error , 0x309.0 for enable this function 1 for g uality , read - back data if ?1? indicate input data decode ma ybe is error , 0x309.0 for enable this function 0 for b uality , read - back data if ?1? indicate input data decode maybe is error , 0x309.0 for enable this function default: 0000 0000b 0x309 dvi auto equalize - 3 r/w bits name description 7 - 1 reserved 0 dvi decode data check , write ? 1 ? and if read back ? 0 ? mean is ready for 0x308 read back 0: disable 1: enable default: 0000 0000b 0x310 dvi auto equalize - 4 r/w bits name description 7 - 0 set 0x13 for 0x317 ~ 0x31b read - back function b it - 0 write ? 1 ? and if read back ? 0 ? mean is ready for 0x317 ~ 0x31b read back default: 0000 0000b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 137 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x311 dvi auto equalize - 5 r/w bits name description 7 - 0 set 0x55 for 0x317 ~ 0x31b check cycle is 1v default: 0000 0000b 0x317 ~0x31b dvi auto equalize - 6 r bits name description 7 - 0 dvi eye diagram quality check , more continue ?0? mean is better signal uality . set 0x01e is ?0x08 ~ 0x38? , ?0xbf? , ?0xef? , ?0xff? to get better setting . default: 0000 0000b 0x3 38 dvi ac couple r/w bits name description 7 dvi cl k ac couple 0: disable 1: enable 6 - 4 dvi rgb ac couple 0: disable 1: enable 3 - 0 reserved default: 0 111 11 00b 8.28. dithering function 2 0x370 dither block blending control r/w bits name description 7 lsb 10_blend_type 0: static and dynamic ordered blending . 1: random and dynamic ordered blending . 6 lsb01/11_blend_type 0: static and dynamic ordered blending . 1: random and dynamic ordered blending . 5 lsb10_blend_en 0: disable . 1: enable . 4 - 3 lsb1 0_blend_logic_op 00: or . 01: xor . 10: xor . 11: and . 2 lsb01/11_blend_en 0: disable . 1: enable . 1 - 0 lsb01/11_blend_logic_op 00: or . 01: xor . 10: xor . 11: and . default: 0000 0000b 0x371 dither toggle / mix control r/w bits name description 7 reserved 6 mix_3in1_dither_en( b ) , 0x371 .1 must set ? 1 ? 5 mix_3in1_dither_en ? , 0x371 .1 must set ? 1 ? free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 138 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 4 mix_3in1_dither_en(g) 3 - 2 reserved 1 0: r/g/b control depends on g channel 1: use separate control registers 0 block_toggle_en 0: disab le . 1: enable . .( 0x370 blend must enable ) default: 0000 0000b 0x372 separate r dithering control - 1 r/w bits name description 7 - 4 r channel ?10? dithering option , 0x371.1 must set ?1? 3 - 0 r channel dither mode , , 0x371.1 must set ?1? default: 0 000 0000b 0x373 separate r dithering control - 2 r/w bits name description 7 - 6 reserved 5 mixed dither enable 4 dynamic dither 3 - 2 dynnmic mode [1:0] 1 - 0 static mode [1:0] default: 0000 0000b 0x374 separate r dithering control - 3 r/w bits n ame description 7 lsb10_blend_type 0: static and dynamic ordered blending . 1: random and dynamic ordered blending . 6 lsb01_blend_type 0: static and dynamic ordered blending . 1: random and dynamic ordered blending . 5 lsb10_blend_en 0: disable . 1: en able . 4 - 3 lsb10_blend_logic_op 00: or . 01: xor . 10: xor . 11: and . 2 lsb01_blend_en 0: disable . 1: enable . 1 - 0 lsb01_blend_logic_op 00: or . 01: xor . 10: xor . 11: and . default: 0000 0000b 0x375 separate b dithering control - 1 r/w bits name de scription 7 - 4 b channel ?10? dithering option , 0x371.1 must set ?1? 3 - 0 b channel dither mode [3:0] , , 0x371.1 must set ?1? default: 0000 0000b 0x376 separate b dithering control - 2 r/w bits name description free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 139 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7 - 6 reserved 5 mixed dither enable 4 dynamic dither 3 - 2 dynnmic mode [1:0] 1 - 0 static mode [1:0] default: 0000 0000b 0x377 separate b dithering control - 3 r/w bits name description 7 lsb10_blend_type 0: static and dynamic ordered blending . 1: random and dynamic ordered blending . 6 lsb01_blend_type 0: static and dynamic ordered blending . 1: random and dynamic ordered blending . 5 lsb10_blend_en 0: disable . 1: enable . 0x371.0 must set ? 1 ? 4 - 3 lsb10_blend_logic_op 00: or . 01: xor . 10: xor . 11: and . 2 lsb01_blend_en 0: d isable . 1: enable . 0x371.0 must set ? 1 ? 1 - 0 lsb01_blend_logic_op 00: or . 01: xor . 10: xor . 11: and . default: 0000 0000b 0x378~0x37f : reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 140 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 8.29. horizontal non - linear scaling function slope1 center point zone2 slope2 non-linear position zone1 display active window 0x380 horizontal non - linear scaling control r/w bits name description 7 - 1 reserved 0 nl_scaling_en 0 = normal linear scaling applied to entire image. 1 = enable non - linear scaling ( 16:9 display zoom ratio ) default: 0000 0000b 0x381 non - linear scaling offset adjust r/w bits name description 7 - 0 nl_off[7:0 ] adjust the error for scaling factor. default: 0000 0000b 0x382 non - linear scaling factor zone1 end ? low byte r/w bits name description 7 - 0 nl_zone1_end [7:0] sets the scaling factor in the first non - linear scaling region (zone1). default: 0000 0000 b 0x383 non - linear scaling factor zone1 end ? high byte r/w bits name description 7 - 0 nl_zone1_end [15:8] sets the scaling factor in the first non - linear scaling region (zone1). default: 0000 0000b 0x384 non - linear scaling zone1 slope ? low byte r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 141 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bi ts name description 7 - 0 nl_slope1 [7:0] sets the slope factor in the first non - linear scaling region (zone1). default: 0000 0000b 0x385 non - linear scaling zone1 slope ? high byte r/w bits name description 7 - 0 nl_slope1 [15:8] sets the slope factor in t he first non - linear scaling region (zone1). default: 0000 0000b 0x386 non - linear scaling factor zone2 end ? low byte r/w bits name description 7 - 0 nl_zone2_end [7:0] sets the scaling factor in the first non - linear scaling region (zone2). default: 0000 0000b 0x387 non - linear scaling factor zone2 end ? high byte r/w bits name description 7 - 0 nl_zone2_end [15:8] sets the scaling factor in the first non - linear scaling region (zone2). default: 0000 0000b 0x388 non - linear scaling zone2 slope ? low byte r/w bits name description 7 - 0 nl_slope2 [7:0] sets the slope factor in the first non - linear scaling region (zone2). default: 0000 0000b 0x389 non - linear scaling zone2 slope ? high r/w bits name description 7 - 0 nl_slope2 [15:8] sets the slope factor in th e first non - linear scaling region (zone2). default: 0000 0000b 0x38a non - linear position ? low byte r/w bits name description 7 - 0 nl_cbeg [7:0] sets the position of zone1 and zone2. default: 0000 0000b 0x38b non - linear position ? high byte r/w bits na me description 7 - 0 nl_cbeg [15:8] sets the position of zone1 and zone2. . default: 0000 0000b 0x38c~0x38f : reserved 8.30. bright frame border function 0x390 bright frame windows border control r/w bits name description 7 bf1_border_ en bf1 border 0 = disa ble 1 = enable free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 142 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6 bf2_border_ en bf2 border 0 = disable 1 = enable 5 reserved 4 gamma_position_sw switching gamma position 0: after osd block 1: before bf block 3 bf2_ yuv2rgb _en bf2 yuv to rgb color space 0 = disable. 1 = enable 2 bf2_rgb2yuv_ e n bf2 rgb to yuv color space 0 = disable. 1 = enable 1 bf1_yuv2rgb _en bf1 yuv to rgb color space 0 = disable. 1 = enable 0 bf1_rgb2yuv_ en bf1 rgb to yuv color space 0 = disable. 1 = enable default: 0000 0000b 0x391 bright frame border r color contr ol r/w bits name description 7 - 0 bf_border_r[7:0] bright frame border color r[7:0] . default: 0000 0000b 0x392 bright frame border g color control r/w bits name description 7 - 0 bf_border_g[7:0] bright frame border color g[7:0] . default: 0000 0000b 0 x393 bright frame border b color control r/w bits name description 7 - 0 bf_border_b[7:0] bright frame border color b[7:0] . default: 0000 0000b 0x394 bright frame border enable control r/w bits name description 7 - 3 reserved 2 bf_border_top/bo t bright frame top/bottom border enable control 0: disable 1: enable. 1 bf_border_right bright frame right border enable control 0: disable 1: enable. 0 bf_border_left bright frame left border enable control 0: disable 1: enable. default: 0000 0000b 0x395 ~0x399 : reserved free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 143 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x39a sub - pixel dither control r/w bits name description 7 pattern 025_1 enable 6 - 4 pattern 025_0 enable 2 10_subpixel pattern 05 sub - pixel enable , 0x371.4 set ?1? 1 01_subpixel pattern 025 sub - pixel enable , 0x371.4 set ?1? 0 mix_enable enable mix mode default: 0000 0000b 0x39b sub - pixel dither control r/w bits name description 7 - 5 pattern 025_3 enable 4 - 2 pattern 025_2 enable 1 pattern 025_1 enable 0 pattern 025_1 enable default: 0000 0000b 0x39c sub - pixel dithe r control r/w bits name description 7 - 0 pattern 05 enable default: 0000 0000b 0x3 9d mix dither mode control r/w bits name description 7 - 6 reserved 5 static_cnt[2] static dithering active period counter for b channel 0x376[5:4] set ? 11 ? 0x376 [3:2] f or static_cnt[ 1:0 ] 0x371[1] must set ? 1 ? 4 random_cnt[2] random dithering active period counter for b channel 0x376[5:4] set ? 11 ? 0x376 [1:0] for random _cnt[ 1:0 ] 0x371[1] must set ? 1 ? 3 static_cnt[2] static dithering active period counter for g channel 0 x1da[5:4] set ? 11 ? 0x1da[3:2] for static_cnt[ 1:0 ] 2 random_cnt[2] random dithering active period counter for g channel 0x1da[5:4] set ? 11 ? 0x1da[1:0] for random _cnt[ 1:0 ] 1 static_cnt[2] static dithering active period counter for r channel 0x373[5:4] set ? 11 ? 0x373 [3:2] for static_cnt[ 1:0 ] 0x371[1] must set ? 1 ? 0 random_cnt[2] random dithering active period counter for r channel 0x373[5:4] set ? 11 ? 0x373 [1:0] for random _cnt[ 1:0 ] 0x371[1] must set ? 1 ? default: 0000 000 0b 0x3 9e mix 3 in 1dither mode cont rol r/w free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 144 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. bits name description 7 - 6 reserved 5 - 4 r_mix3_type mix 3 in 1 dithering mode random type for r channel 0x373 set ? 0x00 ? 0x371 set ? 0x72 ? 00: original (4/16 random) 01: 1/16 random 10: 2/16 random 11: reserved 3 - 2 reserved 1 - 0 g_mix3_type m ix 3 in 1 dithering mode random type for g channel 0x1da set ? 0x00 ? 0x371 set ? 0x72 ? 00: original (4/16 random) 01: 1/16 random 10: 2/16 random 11: reserved default: 0000 000 0b 0x3 9f mix 3 in 1dither mode control r/w bits name description 7 - 2 reserved 1 - 0 b _mix3_type mix 3 in 1 dithering mode random type for b channel 0x376 set ? 0x00 ? 0x371 set ? 0x72 ? 00: original (4/16 random) 01: 1/16 random 10: 2/16 random 11: reserved default: 0000 000 0b 8.31. y/c peaking control high pass filter throshold gain + y/c peaking block 0x3a0 y/ c peaking function control r/w bits name description 7 - 6 reserved 5 chroma_peak_median_en these bits set the chroma median peaking control. (average cb,cr high pass value) 0: disabled 1: enabled 4 chroma_peak_en these bits set the chroma peaking control. (cb,cr high pass) 0: disabled free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 145 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 1: enabled 3 - 2 reserved 1 text_enhance text enhance , the priority higher than luma_peak_en 0: disabled 1: enabled 0 luma_peak_en this bit enables the luma horizontal peaking control , 0: disabled 1: ena bled default: 0010 0000b 0x3a1 luma peaking range control r/w bits name description 7 - 4 ycoring[3:0] to contr ol lum a sig nal thr oshold ( cor ing ) 3 - 2 ygain[1:0] luma gain range control y peaking : 1/2 , 1, 2 , 4 1 - 0 yfreq[1:0] to contr ol lum a f r eq r ange . default: 0000 0000b 0x3a2 chroma peaking range control r/w bits name description 7 - 4 ccoring[3:0] to contr ol chr om a sig nal t hr oshold . 3 - 2 cgain[1:0] to contr ol chr om a g ain r ang e . 1 - 0 cfreq[1:0] to contr ol chr om a f r eq rang e . default: 0000 0000b 0x3a3 text enhance control r/w bits name description 7 - 0 lum_noise_thd[7:0] luminace noise threshold recommended value to 20h (10 bits) d efault: 00 1 0 0000b 0x3a4 text enhance control r/w bits name description 7 double_text_enhance text en hance double effect 6 - 4 luma_gain luminance gain level 1 - 0 chroma_thd[1:0] chrominance threshold level, higher level enhances more color pixels 00: 128 01: 256 10: 512 11: 1024 default: xxxx xx11 b 0x3a5~0x3af : reserved 8.32. ace con trol 0x3b0 ace function control r/w bits name description 7 reserved 6 non_linear_mode enable non - linear histogram mode ( only support bf1 ) 5 data_port_sel[1] data port access selection, this bit sett ing will reference to reg. 0x3b1[4], {3b0[5], 3b1[4]} free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 146 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 00 : histogram read, 01 : i - gamma curve r/w 1x : non - linear histogram point r/w 4 hist_mode 0: mode 0 , pixel number accumulation mode . 1: mode 1 ,frame number accumulation mode . 3 - 2 ace_mode[1:0] 0 0: 4 area histogram / i ? gamma curve . 01: 8 area histogram / i ? gamma curve . 10: 16 area histogram / i ? gamma curve . 11: reserved 1 bf1_i - gamma_en bf1 , i - gamma function 0: disable 1: enable 0 bf2_i - gamma_en bf2 , i - gamma function 0: disable 1: en able default: 0000 0000b 0x3b1 ace function control r/w bits name description 7 i - gamma_update 1: for update i - gamma curve data . 6 i - gamma_rw 0: read i - gamma curve . 1: write i - gamma curve . 5 winsel 0 : for bf1 access . 1 : for bf2 access . 4 data_port_sel if reg. 0x3b0[5] set to 0 1: for i - gamma curve r/w, 0: for histogram read. if reg. 0x3b0[5] set to 1, the data port will access non - linear histogram point r/w 3 - 1 frame_mode[2:0] 000 ~ 111: for 1 to 255 frame calculation . 0 hist_en/hist _rdy 0: histogram read ready 1: enable histogram default: 0000 0000b histogram read : 4 or 8 or 16 area pixel counts in entire frame , if hist_mode set ?0? histogram read : 4 or 8 or 16 area over threshold frame counts in 256 frame , if hist_mode set ? 1? 0x3b2 ace r/w data port r/w bits name description 7 - 0 data_port[7:0] ace r/w data port[7:0] default: 0000 0000b 0x3b3 frame mode threshold ? low byte r/w bits name description 7 - 0 frame_threshold[7:0] mode 1 threshold [7:0] default: 0000 00 00b 0x3b4 frame mode threshold ? mid byte r/w bits name description 7 - 0 frame_threshold[15:8] mode 1 threshold [15:8] free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 147 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. default: 0000 0000b 0x3b5 frame mode threshold ? high byte r/w bits name description 7 - 0 frame_threshold[23:16] mode 1 threshol d[23:16] default: 0000 0000b 0x3b6~0x3bf : reserved 8.33. color management 0x3c0 cm color adjustment control r/w bits name description 7 cm_update_flag the status of updating new coefficients to controller right after any write to brightness, contrast, intens ity, hue, and saturation. this flag is read - only bit. 0: done 1: busy 6 cm_bright_en brightness adjust function enable, update adjustment in vsync 0: disable 1: enable 5 cm_contrast_en contrast adjust function enable, update adjustment in vsync 0: di sable 1: enable 4 cm_hue_en hue adjust function enable, update adjustment in vsync 0: disable 1: enable 3 cm_saturation_en saturation adjust function enable, update adjustment in vsync 0: disable 1: enable 2 cm_intensity_en intensity adjust function ena ble, update adjustment in vsync 0: disable 1: enable 1 - 0 reserved default: 0000 0000b 0x3c1 cm brightness coefficient for red r/w bits name description 7 - 0 cm_brightness_r this parameter is active when cm_bright_en is active. the value is from ? 128 to 127 in 2?s complement, power on default is 0. r display color = (original value * contrast coef.) + brightness coef. default: 0000 0000b 0x3c2 cm brightness coefficient for green r/w bits name description 7 - 0 cm_brightness_g this parameter is active when cm_bright_en is active. the value is from ? 128 to 127 in 2?s complement, power on default is 0. g display color = (original value * contrast coef.) + brightness coef. default: 0000 0000b 0x3c3 cm brightness coefficient for blue r/w bits name descrip tion free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 148 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7 - 0 cm_brightness_b this parameter is active when cm_bright_en is active. the value is from ? 128 to 127 in 2?s complement, power on default is 0. b display color = (original value * contrast coef.) + brightness coef. default: 0000 0000b 0x3c4 cm con trast ratio coefficient for r r/w bits name description 7 - 0 cm_contrast_r this parameter is active when cm_contrast_en is active. the value is from 0(00 h) to2 (ff h), power on default is 1 (80h).. default: 1000 0000b 0x3c5 cm contrast ratio coefficient for g r/w bits name description 7 - 0 cm_contrast_g this parameter is active when cm_contrast_en is active. the value is from 0(00 h) to2 (ff h), power on default is 1 (80h). default: 1000 0000b 0x3c6 cm contrast ratio coefficient for b r/w bits name de scription 7 - 0 cm_contrast_b this parameter is active when cm_contrast_en is active. the value is from 0(00 h) to2 (ff h), power on default is 1 (80h). default: 1000 0000b 0x3c7 cm hue coefficient r/w bits name description 7 - 0 cm_hue this parameter is active when cm_hue_en is active. the value is from 00h to 7fh, one step means 180/128 degree. bit 7 is sign bit: 0: clockwise (negative rotation), 1: counterclockwise (positive rotation) default: 0000 0000b 0x3c8 cm hue coefficient r/w bits name des cription 7 - 0 cm_saturation this parameter is active when cm_saturation_en is active. the value is from 00 h to ff h. default: 1000 0000b 0x3c9 cm hue coefficient r/w bits name description 7 - 0 cm_intensity this parameter is active when cm_intensity_en is active. the value is from 00 h to ff h. (0~2) default: 1000 0000b 0x3ca~0x3cb : reserved 0x3cc cm color enhancement configuration r/w bits name description 7 hh_map_en hue - hue map 0: disable 1: enable free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 149 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 6 hs_map_en hue - saturation map 0: disable 1: enable 5 ss_map_en saturation - saturation map 0: disable 1: enable 4 - 2 reserved 1 map_load_en mapping table load enable 0: disable 1: enable 0 cm_ce_en cm color enhancement enable , 0: disable 1: enable default: 0000 0000b 0x3cd cm index access port control r/w bits name description 7 - 2 reserved 1 - 0 cm_index_sel table select : 00: no access, 01: hue - hue table, 10: hue - saturation table 11: saturation - saturation table default: 0000 0000b 0x3ce cm index access port address r/w bits name description 7 - 5 reserved 4 - 0 cm_index_ addr table addr ess: hue - hue address: 0~23 (24 entries), each step means 15 degree hue - saturation address: 0~23 (24 entries), each step means 15 degree saturation - saturation address: 0~16 (17 entries), eac h step means 1/16 full saturation scale default: 000 0 001 0 b 0x3cf cm index access port r/w bits name description 7 - 0 cm_index_port hue - hue data port: the value is from 00h to 7fh, one step means 30/128 degree. bit 7: 0 is clockwise, 1 is counterclock wise. power on default is 00h. hue - saturation data port: the value is from 00h to ffh. (0~2). power on default is 80h (1). saturation - saturation data port: the value is from 00 h to ff h. (0~1). power on default is ffh (1). default: 0000 0000b(hh), 10 00 0000b(hs),1111 1111b(ss) 0x 3d0 ~0x 3fe : reserved 0x 3 ff accessing register page enable r/w bits name description free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 150 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7 - 2 reserved 1 - 0 reg_page_sel register page enable 00 0 : enable register page0. 0 0 1: enable register page1. 0 10: enable register pa ge2. 0 11: enable register page3. 100 : enable register page 4 . default: 0000 0000b 0x 400 ~0x 42f : reserved 8.34. dbc 0x 430 dbc control r /w bits name description 7 - 4 abrupt_thd[3:0] when abrupt_change_enable =1, if the differences of the current and previous fr ame statistics are bigger than abrupt_th*16, it will considered as un - stable immediately. 3 abrupt_en abrupt_change_enable: 1: abrupt change function enabele 0: abrupt change function disabled 2 dbc_dith_en dbc_dither_enable: 1: dbc dither is disabled. 0: dbc dither is disabled 1 dbc_data_en modify rgb value according to pwm value 1: enable modification 0: disable (no change) 0 dbc_bl_con_en dynamic backlight control enable (pin selection by reg0ee[5]) 1:enable 0:disable default: 1111 0100 b 0x 431 db c adjust r /w bits name description 7 - 4 duty_adj_rate dynamic backlight control adjustment rate. pwm and color values will adjusted according to frame statistics at every (adjust_rate+1) stable frames 3 - 0 duty_adj_step pwm duty adjustment step size: the maximum step size when adjust the pwm duty at the adjust frame rate default: 1000 0011 b 0x 432 pwm min r /w bits name description 7 - 0 dbc_pwm_min the lower bond of pwm duty cycle. no matter how pwm duty is modified according to frame statistics. the duty cycle will never lower than pwm_min/256. pwm_min must be no smaller than 8?h40. default: 1000 0000 b 0x 433 pwm divider 1 r /w bits name description free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 151 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 7 - 6 dbc_pwm_duty_msb [1:0] used to add , 0/4, 1/4, 2/4,3/4 with duty[7:0]/1024 5 dbc_pwm_pol pwm polarity control 1: invert 0: normal 4 reg_vsync_mode load pwm control register on display vsync leading edge 3 - 0 dbc_pwm_div1 first divider -- pwm clock divide of the selected clock by 0000 = 1; 0001 = 2 ; 0010 = 4 ; 0011 = 8 ; 0100 = 16 ; 0101 = 32 ; 0110 = 64 ; 011 1 = 128 ; 1000 = 256 ; 1001 = 512 ; 1010 = 1024 ; 1011 = 2048 ; 1100 = 4096 ; 1101 = 8192 ; 1110 = 16384 ; 11=16384 ; default: 0000 0111 b 0x 434 pwm divider 2 r /w bits name description 7 - 0 dbc_pwm_div2 dbc pwm period counter value. 1~256 default: 0101 0100 b 0x 435 pwm divider 2 r /w bits name description 7 - 0 dbc_pwm_duty [7:0] dbc pwm duty. 0.39% ~ 100% , (pwmb_duty[7:0] + 1)/256x100% default: 1111 1111 b 0x 436 dbc pwm control r /w bits name description 7 dbc_pwm_en dbc pwm function enable 6 pwm a (pwm 0 ) dbc pwm function apply to pwm a 5 pwm b (pwm 1 ) dbc pwm function apply to pwm b 4 ave_saving_mode when ave_saving_mode=1, the power saving ratio is determined by average and maximum color in the frame 3 - 0 allow_distort when distort is not ?00?, the color value of ?255 - distortx2? to 255 might to mapping to the same value default: 0000 0000 b 0x 437 pwm offset r bits name description 7 - 0 pwm_offset dbc pwm offset control default: xxxx xxxx b 0x 438 y ave r bits name description 7 - 0 y_avearge the average value of l uminance of the current frame. it is updated every frame and used for image stable criterion d efault: xxxx xxxx b 0x 439 effective color value r bits name description 7 - 0 effe_color effective color value for dbc control default: xxxx xxxx b free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 152 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 0x 43a rgb comp ensator value r bits name description 7 - 0 rgb_compen[7:0] rgb compensator default: xxxx xxxx b 0x 43b pwm act r bits name description 7 - 0 pwm_act[7:0] it is the final duty cycle value of pwm after dynamic backlight control. in fact pwm_act = pwm_set * max_color/256 default: 0000 0000 b 0x 43e dbc index port control r /w bits name description 7 - 6 reserved 5 - 4 dbc_table_sel 00: none 01: y gray to lightness mapping table 10: pwm to lightness mapping table 11: pw m ration to multiplier mapping table 3 - 1 reserved 0 port_rw port read/write 0: write 1: read default: 0000 0000 b 0x 43f dbc index data port r /w bits name description 7 - 0 port_data[7:0] dbc table r/w data port [7:0] default: 0000 0000 b 0x 440 ~ 0x4fe: reserved register 0x 4 ff accessing registe r page enable r/w bits name description 7 - 3 reserved 2 - 0 reg_page_sel register page enable 00 0 : enable register page0. 0 0 1: enable register page1. 0 10: enable register page2. 0 11: enable register page3. 100 : enable register page 4 . free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 153 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 9. ordering information order code package note nt68667 fg qfp 128l pb free nt68667 h fg qfp 128l pb free nt68667 u fg qfp 128l pb free free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 154 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. package information qfp 128l outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol min nom max min nom max a -- -- 0.134 -- -- 3.40 a1 0.010 -- -- 0.25 -- -- a2 0.101 0.112 0.117 2.57 2.85 2.97 b 0.005 0.009 0.011 0.13 0.22 0.27 c 0.004 -- 0.008 0.09 -- 0.20 d 0.906 0.913 0.921 23.00 23.20 23.40 d1 0.783 0.787 0.791 19.90 20.00 20.10 e 0.669 0.667 0 .685 17.00 17.20 17.40 e1 0.547 0.551 0.555 13.90 14.00 14.10 e 0.020 bsc 0.5 bsc l 0.029 0.035 0.041 0.73 0.88 1.03 l1 0.063 bsc 1.60 bsc y -- -- 0.004 -- -- 0.10 ? 0 -- 7 0 -- 7 notes: 1.dimensions d & e do not include resin fins. 2.dimensions f, gd & ge are for pc board surface mount pad pitch design reference only a 1 a 2 a seating plane y 0.10 detail "a" see detail "f" d 1 102 d e 103 e 65 128 64 39 38 1 e 1 b ? l 1 g g gage plane 0.25mm detail f l b c with plating base metal detail a 0~8 degree (4x) 0~8 degree (4x) free datasheet http:///
nt686 6 7 h/ nt68667 scaler 2008 - 05 - 05 155 ver. 1. 5 with respect to the information represented on this website, novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a partic ular purpose, non - infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. 1 trail : 66 pcs 1 box : 10 trail 1 carton : 6 box free datasheet http:///

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